I received a design from a vendor, which is designed for Virtex 2 FPGA. In the design there are four instances of RAMs, which are of DPRAMs of
16bX4096w each. (In fact, there are no WRITE events to these RAMs throughout simulations.)In the test bench, a FOR loop reads in some ASCII files and pumps into RAMs at beginning of each simulation.
Now when I convert this portion into ASIC using library RAMs, how should I take care of this?
Thank you for your comments.