gated clock

Patrick, Are the two clocks asynchronous? Cheers, Syms.

no there are synchronous

if reset then reset_stuff_happens_here; elsif rising_edge(fast_clock) then if clock_mode = 0 then --which clock to use? clock_en

in fact I want to send the CLK clock to all the design not just a FSM So CLK_1 goes to filter one, filter two, etc and then it's CLK_2 that goes to filter one, filter two (filters with others coefficients in respect to the new clock CLK_2)

I think you want to send a single fast clock to filter one, filter two. If necessary, make it with a PLL or DCM. Then use a clock enable for the filters. Adjust the clock enable according to your required rates.

Assuming you are not switching clocks at any random time creating some undesired pulse in the output of the MUX, or that if you do, you are resetting the whole circuit after switching clocks, you can simply ignore the warning.

We give you a warning because the Timing Analyzer does not know if this was intended or not, but we know this can create a static hazard. But you are the designer and know better if this is safe or not based on your intended behavior.

Note that the Classic Timing Analyzer will assume four domains when computing slack:

CLK_1->CLK_1 CLK_1->CLK_2 CLK_2->CLK_1 CLK_2->CLK_2

Simply add the following two QSF assignments to cut the cross-clock domains (again, assuming all registers are clocked by the output of the MUX):

set_instance_assignment -from CLK_1 -to CLK_2 -name CUT ON set_instance_assignment -from CLK_2 -to CLK_1 -name CUT ON

Hope that helps,

- David karchmer Altera Corp.