Ignoring all the paranoid nonsense that is being posted about this, I was able to Google search and find at least one potential PHY from Atmel, the AT78C5091. They have a summary data sheet although I don't see a full sheet. They provide a contact which I assume means they will only sell it if you are interested in high volumes.
It may well be that external PHY chips are not used because of the high power or the high data rate. It would be a lot cheaper and lower power to integrate the PHY into your controller chip.
ummm ... yes and no. The test equipment has a specific bandwidth (either from front end filters, or from FFT resolution) and a specific integration time, both of which can be, and are likely to be, affected by the spread spectrum effects.
The mV/m^2 remains the same, it's just time shifted across the 30KHz bandwidth, with the assumption that is less evil. Which is the case for signals that are integrated at 15KHz and below. At the reciever, the MV/m^2 power from all sources is summed. Without spread spectrum, two interference sources would have to have the same frequency to sum. With spread spectrum they sum if within 30KHz of each other (or whatever the spreading bandwidth is).
However, for data rate signals with symbol times greater than 30KHz, the symbol decoder is integrating at a much faster rate, and the 30KHz shift is a full power interference for one or more symbol times.
For recievers which are wide band, such as most data modems, the 30KHz shift keeps the same mV/m^2 energy completely inside the channel that is a MHz wide or two. The spread spectrum doesn't reduce the interference at all, and may actually make it worse by additively being integrated with non-spread spectrum narrow channel power sources, taking the peak power at a specific frequency above what the reciever can reject.
oh there are "product briefs" for SATA PHY's available from many different vendors. but have you ever tried to purchase a SATA PHY IC? try! and let us know if you succeed!
Atmel has three devices on their HDD page and I am confident that they offer them for sale. I expect that if I wanted to buy a million they would be readily available. The OP did not say how many he expects to use so I am just providing a potential source. What they cost will depend on how many he wants.
Guess I'll have to go look into that as well. I was going to bid an SATA controller design based on the mistaken assumption that since the XUP Virtex-II Pro board had SATA interfaces, that it would be relatively easy to include in the design. Even picked up one of these expensive XUP development systems to prototype it with. Let's just say that this insight was timely, and after the whining by Austin/Antti about the SATA-IO NDA's it's about time to cut my losses with Xilinx and pickup some Altera software and development boards. I'm getting real tired of wasting money on Xilinx products which do not work.
Maybe Altera will listen to this, join SATA-IO and license the IP for it's next product turn.
Ok asshole (sorry folks, I did count to ten, a bunch of times). Since you are so free with your caustic insults and "free advice", including the go fly a kite BS ... let's put this in perspective.
You and Austin have the gaul to whine about NDA's ... consider that Xilinx will not even relax any software interface IP for obsolete products that they refuse to provide full support for, so that Open Source and pickup the mess. Even on new products, they complain openly that they can not provide support for certain market segments because it's not profitable, and would be unfair to the stock holders. The are in over their heads turning new products at a breakneck speed, and drop the previous generations support before they even stop shipping the last of it.
Xilinx doesn't give away much for free, as most forprofits are expected. And at the same time is completely hostile to open source support for XC4K parts, XC3K parts, Spartan parts, etc which they refuse to provide full support for. The offer to Xilinx was to provide open source support to it's customers for these old products, in fact, any product older than two generations back. They are so tight fisted about this, they prefer their customers and their end users have NO support at all, so they will migrate up and trash the old product.
I can not think of a less customer friendly policy, a less deserving company to whine about free SATA IP access. So what is the whining about SATA-IO NDA crap really mean?
Now, we have an open industry wide standards organization, with open membership, and Xilinx refuses to participate complaining the product of that organization doesn't provide free documentation and IP access.
I can think of a lot of terms to describe this self serving bull shit that you two are bitching about. Hypocrites is at the top of the list.
You want to insult me as being Mr Brass? .... just where do you two get off with such crap?
You want to insult me as not having the right to make comments about the vendors not really caring about Xilinx and SATA ... and you two bitch about a non-existant exclusion conspiracy like you are Gods and can read all their minds .... and you can not even follow your own sick BS.
Both of you sound like two spoiled little brats bitching having to pay your fair share like everyone else.
As a Xilinx customer burned by the drop of VHDL/Verilog access to XC4085/XC4062 parts a few years back, I think their support policy for old products is a total travesty. I bought tens of thousands of dollars worth of new and old XV4K parts just as this happened, and got burned bad.
But I stuck with the company. For the last 6 months Austin and Peter have been a shining example of why purchasing the next $30K of Virtex, Virtex-E, Virtex-II and Virtex-Pro parts was a horrible mistake.
Xilinx just plain sucks as an arrogant customer insensitive corporation gone awry. That you lackeys just compound that to gain good graces, and to hopefully pickup some crumbs of support, is just a crying shame.
Xilinx simply doesn't have problems ... it is the problem.
As a new owner of XUP V2Pro board, my comment is that Xilinx screwed up royally by not joining the standards process BEFORE shipping a SATA based product or design. I purchased the board simply BECAUSE it had these interfaces.
There are certain expectations that systems vendors actively take part in industry standards if they are going to ship and support products based on those standards. I've spent years of my life supporting standards processes ... they are the most valuable customer asset a systems company can invest in to protect both their products, their customers products, and a safe product migration path over time.
I can't say anything about their support of mature products. They will continue to sell parts, but yes, they don't provide much support. But the issue of open documentation on SATA, is that about the cost to Xilinx or the cost to their customers? I can see where they would not want to work with a standard that makes it difficult for their customers to get documentation. I can't say I have ever seen IP offered for free other than at opencores.org. Did Xilinx really complain that the SATA IP is not free?
schrieb im Newsbeitrag news: snipped-for-privacy@h48g2000cwc.googlegroups.com...
Hi John,
well I was in about the same situation as you, namly I recommended the purchase of ML300 (4695 USD !!) for an project, and I assumed that the SATA can be use don that board. Well Xilinx response was "Sure we thest the SATA on ML300! We use the BERT test application and loopback cable!" - you can imagine I wasnt very happy with such a response. At that time when that purchasing decison was made (base on my recommendatio) Xilinx MGT documentation listed SATA as on of the supported protocols. The updated MGT docs do not include SATA anymore.
good god, I just checked the ML300 latest documentation and it still lists: "The ML300 provides for operation as a Serial ATA host or device." This is of course not true. Ok it must be that the ML300 docs have not been updated.
Now to the XUP V2Pro board, first of all this board is designed made by digilent, so whatever is screwed up as you say with this board then its done by digilent, and not Xilinx. With the XUP board the SATA is a little better than with ML300 as the OOB fixup is added to the XUP (its missing on ML300) see page 29 of the XUP board schematic.
The OOB can be done without the FET solution too when rx and tx are used from different MGT (not possible on ML300) I have tested that on Memec VP20 board where I did succesfull got past the OOB handshaking and was seeing the inband signalling from the Silicon Image SATA chip.
So you should be also able to get SATA working on XUP. There isnt much ready IP for that, thats another question. And if you are considering an commercial product that has to pass __full__ compliance then I see no alternatives as using a external SATA-PATA bridge, it save you both development time and actual self cost of the product as well (relative cost of the SATA IP in terms of % of the FPGA is hihger than the SATA-PATA IC).
And again, you can not blaime Xilinx in everything, sure it would be nice to use MGTs for SATA, and a free SATA IP core would be nice too, but - if you really read Xilinx documentation - they are no longer claiming MGTs to handle SATA, so if you missed that, you cant legally say anyhing. Just bad luck for you.
1) DCMs are not used for SATA clock at all, the MGT should be feed with
75MHz reference clock and the SATA data rate clock is recovered in the CDR inside the MGT. So any issues DCM may have are ir-relevant in the regards of SATA
2) the serdes PLL from an wellknown competitor doesn make that serdes more SATA compliant ASFAIK, Stratix-IIGX is not listing SATA as supported standard. LatticeSC is no listing SATA either. Info about Stratix-III and LatticeXP2 is not available yet.
So there just isnt any FPGA silicon devices currently available at all fully confirming to SATA. If you use extenal SATA PHY, then the choice of FPGA is ir-relevant, any decent FPGA should be handle the SATA (after PHY layer)
"Austin Lesea" schrieb im Newsbeitrag news: snipped-for-privacy@xilinx.com...
Hi Austin,
there is still a possibility to get V4FX or V5xxT MGTs to work with SATA gen
1 - the RX and TX MGTs are configured with 4 to 1 datawidht ratio and same ref clock, the RX is configured as full bypass with clock permanently disabled (V4 MGT new feature) . Those the RX would be running at at 6GBit/s, the RX CDR and PCS functions would have to be implemented in FPGA fabric. Not an easy task but doable.
Hmm, maybe. But probably with a hell of logic ressources. If it would be easy, Xilinx would have implemented it into the hard macro, right? But I guess the world (of SATA) is not that bad. AFAIK the spread sprectrum clocking in OPTIONAL and is activated by a register in the drive. So the FPGA application can run fine without spread spectrum option (ok, a metal case will help to fight EMC problems) No big deal at all for me. Comming generations of FPGAs will support spread spectrum stuff.
The XUP board AFAIK is a Xilinx board resold by Digilent, and probably other sources. The board does not have the Digilent name anywhere on it, and the documentation is all Xilinx documentation. I looked at all the available boards before making the choice to use this system to prototype this embedded controller contract.
The terms for the RFQ require full SATA compatability and compliance, which Xilinx has clearly failed to provide at this point. Given Austin's whining, it's pretty clear Xilinx is offering a bait and switch, with no intent of joining SATA-IO and offering a fully certifiable solution for Xilinx designers.
Excuse me .... why not blame Xilinx for the gross missrepresentations in the XUP product? It's clearly their product ... their design (Xilinx Research Labs) and their missleading advertising and documentation. And it's clearly their failure to join SATA-IO if they are offering a SATA solution for Xilinx FPGA designers, and to make sure the documentation for these boards is complete, including the compliance failures.
This is probably the most unethical part of Xilinx, ommissions which suck you and I into wasting valuable time and resources on a completely unusable design strategy.
How do you trust anything, when your supplier has a track record of omissions ... and failure to disclose problem areas .... from valid (meets ISE timing reports) designs failing on parts, to lack of SATA compliance of reference designs?? And then compound that with Austin's and Peter's overt denial of problems in this forum, till cornered.
"Lost, Totally" (as Austin ridicules) .... is Xilinx, Austin, and Peter.
Hi Martin ... would like to share an email reply I got from someone who seems to be a bit gunshy about publicly suggesting Altera:
"there is not much for Altera to listen too, SATA defenetly works on Altera when using SAPIS PHY. in the regards of making S-3GX serdes directly SATA compliant, sure Altera does it if it technically reasonable. There is no need for Altera to license something. Its just the serdes-pll block characteriscitcs, either they are flexible enough to be use in SATA compliant mode or not."
Something I will certainly be looking into this week. It would be nice if the Altera folks would confirm this specifically, and offer some public confirmation as there seems to be several of us with potential near term design wins for Altera if true.
"Falk Brunner" schrieb im Newsbeitrag news: snipped-for-privacy@individual.net...
Hi Falk,
hmm.. I havent checked that, I actually also assumed that spread spectrum is optional, but I did not check on the spec. So I commented biased on Xilinx assumptions that the spread spectrum clock makes some drivers not useable. Last time I worked with Xilinx SATA I wasnt as far as about to worry about spread spectrum. V2Pro was clearly out SATA of spec because CDR hard lock range as there was no cure to that. This is clearly fixed in V4FX - well maybe we should wait up SEG's comments on this.
1) XUP Board is *not* made by Xilinx, neither is Xilinx claiming it can do SATA
2) At the time SEG designed ML300 V2Pro MGT characterization was possible not completed and/or SEG had no information on the actual useability of SATA on V2Pro. So the only thing to be fixed is one line in ML300 documentation, I think most other Xilinx own referencies to V2Pro-SATA have been fixed. One documentation item not being fixed can be 'just overlooked' by someone.
3) ML405 and ML410 also include SATA - on those boards I would assume it should be useable. However it is also remotly possible they got designed when the FX silicon was not tested as the V4FX MGT testing was finished very late.
in any case - I can not and do not want to belive that Xilinx designed boards with features knowing not to work (at the time of the board design).
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