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Driving a 30 bit wide LVTTL bus at 160MHz

Hello,

In my future design I could win a lot of pins if I could drive a bus at

160MHz. Because of bank restrictions and because this bus is connected to a CPLD, I will have to use LVTTL. Has anybody tried driving a bus in LVTTL at 160MHz?

I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has LVDS CPLDs but only the large CPLDs support LVDS inputs.

I am afraid that this bus will have a lot of EMI/EMC problems. What do you think of it, should series termination be adequate to limit the EMI/EMC problems?

best regards, Dolphin

Reply to
Dolphin
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Reply to
Symon

It can be done with extreme care. Keep the lines short, you may need to terminate them, and by all means do a SI simulation on it so that you know it will work rather than blindly applying "fixes".

Reply to
Ray Andraka

Also be careful of Simulaneously Switching Outputs guidelines. As Ray says it can be done but if you use a crappy package like PQ208 or TQ144 you may have big problems with ground bounce that causes the interface to fail. Most of the BGA packages do much better at this fast type of driving from our experience.

Some CPLDs like the bigger Coolrunner-IIs can also support single ended standards like SSTL, HSTL that are designed for high speed and may be a an alternate solution for you. These standards have the advantage of small signal swings too which is better for ground bounce and EMC.

John Adair Enterpo> Dolph> > Hello,

Reply to
John Adair 

--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
Reply to
Aurelian Lazarut

You mentioned speed, but forgot distance ? How far does this have to go - sounds like the CPLD is a (remote?) slave ? You can get small LVDS-LVTTL transcievers, plus you can also use dual data lines, to halve the clock rate. ( see winbond for dual-data SPI memory, they spec to 150MHz )

-jg

Reply to
Jim Granville

Add a series-resistor in the lines and/or use the current-limiting feature of the I/O-ports (if available). (too reduce the slopes of the signals)

Kind regards, Stef?

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Reply to
Stef?

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