On a sunny day (27 Feb 2006 13:12:21 -0800) it happened "logjam" wrote in :
Normally you could use flip flops as static memory, it would lose state when power goes down. I have seen a very nice memory device (analog at that), it consisted of a small poly cap, on the gate of a CMOS transistor.
It was charged via a neon and resistor (70 V needed to conduct the neon) from a + 100V or -100V via a switch. Believe it or not, it held state for month. This was used in a color tv set to adjust the brightness / contrast / etc.. think it was Siemens, and likely patented (the switches were up-down buttons). So, maybe you can switch with CMOS transistors from normal + and ground. Depends on the leakage, else some neons and some HV transistors should give you this. You can then use a window discriminator to store say 4 bits or more at the time in one poly cap. up +12 --- |
On a sunny day (27 Feb 2006 13:52:19 -0800) it happened "Isaac Bosompem" wrote in :
shows....
It is the 265 kB dynamic RAMdisk. It is addressed as floppy drive B It has its own refresh, the Z80 main memory was originally 64k dynamic ram, but as soon as I could get 32 kB static I replaced the main memory by 2 of those.
Right, no DMA needed for the floppy, but the floppy controller used a FDC8072A (as in IBM PC) and an analog PLL :-) In polling! There is a DMA, but never used it for floppy transfers. The other oddity is the display, i t is IO mapped, has its own memory. The processor has to write a display address and data for each byte via IO. Exactly the same mechanism as the RAM disk, but now with static RAM. I also used the display memory (the invisible part) to store the CCP for warm boot.... Faster :-)
As noted earlier, there are sub-quadratic combinitorial designs for both multiplication and division even when working with basic gates. "Sub-quadratic" refers to the amount of hardware. They are at worst linear in terms of delay.
Note that in two dimensions, quadratic in the amount of hardware implies at least linear in the amount of delay.
I've also used that for 50mil packages, but it's hard to avoid bridging with packages that have finer pitch. BGA's are cool and easy. Solder wet all the pcb bga pads with a solder ball pushed around with the pads slightly over fluxed, so there is a small shiny bump at each pad. Clean pcb, reflux, place BGA with flux covering balls on the pcb pads, and reflow in a convection oven for a few minutes. 300-1700 connections terminated with really only two minutes effort and several more cleaning and watching it bake :)
Most of the early computers I worked with in Dr. Dicky's lab with tubes, were bit serial executing directly off multi-channel read/write from the drums (head per track, and several concurrent channels). It would literally be fetching instruction, data, operating on the data, and writing all at the same time. Track down the schematics for the Bendix G15 - I saw them on the web somewhere last fall. It's a tube based drum computer, but was simple, and they made a lot of them. There is probably some software kicking around for it as well.
I would suggest if you wanted to build a fun transistor computer, to design it bit serial with four IDE hard drives, two of which could be crashed, as long as you could still do diagnositic read/write to it's buffer. Then the computer would just need a hand full of serial/parallel buffers at the edges for the drive interfaces. Or better yet, get some older drives that still have a serial interface, and be really retro :)
Being really retro would be taking a hand full of floppy drives apart for their heads, collecting some 1" mag tape and glue to a cylinder, and building a drum. Or maybe machine up a nice drum, and have it nickle plated, for the real thing :)
The Australian Computer Museum (WA Branch) is rebuilding one.
[snip]
Or salvage some hard drives (the older the better: bigger tracks, larger bit sizes, generally less precision required). Mount the spin motor on a base, spin it up, then use a crystal oscillator & dividers to get a 3-phase supply. Fit up a single platter on the motor, with some additional weight (ie unused platters) as a flywheel, unless you have a truly sinusoidal
3-phase supply (the torque will flutter otherwise). Mount the heads on a fixed platform around the periphery, as head per track. You need a few 10's of mA to drive those heads. You will need some arrangement to lift the heads off the disk when it stops, else the combined stiction of all those heads will see it doesn't start again. Best if you do this by flexing the spring mounting (a fraction of a mm is enough), rather than bodily moving the head mounts; that will upset registration. >
It's not too hard (if you have access to a lathe) to make up the drum, & there's usually a chrome plater's around who will nickel it (that's a prerequisite for chrome plating, anyway). The hard part is making the heads.
I had a working model of the Babbage computer somewhere around 1972 made of plastic. As I recall, it took a fair bit of sanding and lubricating to make it work smoothly. I don't recall who made the kit, or even where I got it.
darn....looked like I missed a good party while I was away... :)
Peter, who -else- would've said they were building a 64b ALU from TTL ?? -Surely- you couldn't have possibly thought it was a commercial design? ROFL... . . One of my best elex learning-experiences was repairing an RCA all-xsistor computer in my teens.
logjam, I know you asked about division in regards to the big ALU; but if you are also thinking about math for your all-transistor computer, you might consider analog techniques as well.
The parts-count and board-space cost would be for an 8b AD/DA implemented in discretes...but the payoff would be pretty fast calc-times...perhaps on the order of single-cycles of the cycle-rate your xsistor cpu is likely to run at (500khz maybe??).
8b accuracy isn't too difficult to achieve in discrete mult/div ckts.
Also, some switch-controlled rewiring can give you trig functions as well...also at single-cycle speeds....
The parts-count for the math-section itself would likely be the same or less than the AD/DA. Of course, with a little thought, you can get either of these functions down to a surprisingly low parts-count. Ramp techniques are extremely simple...with conversion-speed determined mostly by how fast you can count.
And there are topologies which might inherently -combine- both functions into the same parts. There are pulse-based techniques for analog multiplication....quite accurate too...and temp-insensitive; unlike log-element based ckts. I'm just shooting from the hip here, but it seems like this ought to combine nicely with counting-type AD/DA conversion...
For memory logjam, how 'bout DRAM ??
With tiny smt xsistors and caps, you could achieve a reasonable density.
Not as high as core, of course; but finding -undamaged- core planes is getting harder all the time. Sloppy handling always leaves one of those microwires trashed... And besides, you want to build it ALL yourself, right?
I -think- the xsistor-count will still be lower than full static, even after adding the addressing/writing xsistors; but I'm not sure of that. Have never implemented either.
hmmm....it must be getting late; as my mind is drifting over various ways to implement memory with discretes...
how 'bout, instead of using a xsistor-per-bit, you use a differential scheme with only a single diff-amp as sense-amp? Wire all the caps to an X/Y (top/bottom) grid....somewhat like core...an 8b-to-256-line decoder on each side of the grid charges/discharges the selected cap.
With a little thought to the design, you should be able to use 95% of that same decoding parts-group to select a bit/cap for the sense-amp as well....
And with a high enough refresh-rate, you could store a multi-bit value per cap. It would be interesting to see a 256x8 version. At first thought, I felt that 8b would be hard to achieve...but thinking about the scale of this thing....you could easily be using 10-15v signals, and caps of nanofarads rather than femtofarads...so 8b might not be out of reach.
Effectively, you trade mem BW for storage-density...since your refresh-rate will have to scale linearly with the required resolution. i.e. 8b capability requires 4 times less V-sag than 1b (I think)...so
4 times the refresh rate.
hmmm a second time.....you know, you might be able to make a destructive-readout version that wouldn't require any sense-amp and sense-amp decoding at all, as such....
Say you implemented the sense-amp as a -current- sense, within the write drivers themselves. A read-cycle would just be a write-cycle, but with monitoring. If that bit was already charged, there wouldn't be a (normal sized) current-pulse during the write.
I believe such destructive-read methods were the norm in core-memory.
(it's been a looong time since my working-at-DEC days... )
Such a design would really simplify the peripheral circuits. Again, I would look at doing it differentially....so you only have to look for the -direction- of the pulse; rather than measuring magnitude.
Oh, by the way, one more method before I hit the hay...which I was surprised not to see mentioned; given the number of truly knowledgable folks here, and the length of this thread....
Delay Lines.
Some early computing devices used delay-lines as serial storage devices.
Find yourself a 1,000' roll of cheap catv coax at the junkyard for 5 bucks; and there ya go.
8 rolls gives you 8 bits...and if you arrange 'em right, you'll have an interesting modern-art sculpture for the living room...
hmm...actually, speed might be an issue with coax as the medium...
1,000' of coax is only a microsecond or so...and you need a LOT of delay...
It used to be had by using ultrasonic methods via glass delay-lines; some of which are still available, by the way...but which wouldn't be a totally homebrew kind of thing...
Potentially, you could modulate a ghz osc. and beam it at a water-tower 5-10 miles away...that'd give you 20us...
by the way, disks are not just magnetic.... There were several "echo boxes" made as guitar-effects back when, which used an electrostatic technique of some sort on a rotating disk.
hmm....thinking about that reminded me of toner-drums...which reminded me of the earlier mention of machining/coating drums. Toner-drums are electrostatic of course; but may possibly have magnetically-usable properties...
also, CRT's have been used for data-storage... I think they normally were purpose-made, with some sort of electrical readout of the charge on the plate...but you might also work up an optical read method to use with standard CRT's...
pps; on the delay-line method....thinking of ultrasonics....forget solid mediums altogether, and simply -beam- sound at some distant reflector or repeater. 1100' per second, if memory serves...so you could get quite a bit of delay/storage within practical distances.
Although I've never tried it, it's also possible that you could use a
100' roll of, say, 1/2" copper-tubing from the hdw-store as a waveguide. You'd have to have a high-enough frequency to be above cutoff of course...and I'm too zoned to calc that right now. That'd give you roughly 100ms of delay; which might be a fair bit of data...
Old ultrasonic remote-control transducers would work for this app. Direct-tv style parabolic dishes would be suitable for the open-beam technique.. Transducers for depth-sounders ("fish finders") are powerful and fairly high frequency. I'm thinking that the higher the freq, the higher the bit-density and transfer rate you can achieve.
wow....fish-finders....-definitely- time to hit the hay...
ps; I admire what you're doing; and have done similar things myself just for the love of doing it. go for it !
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Or, how about the mercury column? Again, storing bits by whacking the one end of a box filled with merury, and sensing it at the other end?
My favorite is the drum memory for the GR15 tube computer: each instruction had the address of the next one.
That way it didn't matter what order they were in. In fact dropping the deck of cards, and mixing them up sped up execution (a crude but effective interleave).
The mercury delay lines were earlier, and were used only in "mainframes" of that day. Who wants to have a pot full of mercury sloshing around in a cash register? But this was before environmental concerns, when leaded gasoline was the best thing ever...
Did anybody mention the Williams tube? A CRT where you wrote to and read from the tube face. It got killed by the early core memories, which in turn lived much longer than anybody had expected. Non-volatile storage with destructive read-out, just the opposite of SRAM nowadays. Peter Peter
You could say core memory still lives on : in FRAM devices = identical property of magnetic domain storage with destructive read - only they are now manufactured on a wafer, with additional process steps to insert the magnetic domain material, instead of physically wired. [ Bubble memory seems to have hit an evolutionary dead end..]
I also see Intel reckons Ovionic (phase change) memory might yet fly...
Back in my youth, I worked with people who worked with them. You could read the bits off the face of the tube.
Best tale that I remember...
The face of the tubes was round. Memory was 256 square or maybe
512. The software guys were making a lot of noise about needing more memory. (Picture below says 2K bits. Looks like 32x64.)
So the hardware guys added annother address extra bit. Well sort of. Only some of the new locations worked. Those were the ones that fit into the space between the old square and the enclosing circle.
Google is good:
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"hence the official 1.2 millisecond instruction time"
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FRAMs are not magnetic. They use the ferroelectric effect, which is somewhat of a misnomer. They are like core only in that readout is destructive, but the available FRAM chips handle the rewrite internally.
You're probably thinking about MRAMs, which are magnetic. Freescale (formerly Motorola) introduced the MR2A16A 4 Mbit MRAM some time back, but it still doesn't appear to be available through distribution.
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Yes. It worked, but it didn't scale down well, and it was very slow. Commercial devices were made by Hitachi, Intel, TI, and Rockwell. The highest density part was the Intel 7114, which was a 4 Mbit part.
There have been some reports lately that MRAM won't scale well, and thus may also be a dead end. But I think it's too early to write it off.
Many years ago it was claimed that FRAM would be able to achieve comparable densities to DRAM, but that certainly ahs not happened.
Currently highest density NAND flash parts are 8 Gbit. FRAM and MRAM thus have only 1/2048 the density of NAND flash, but are fully random access and have fast read and write times. NAND flash is generally only suited to secondary storage applications (like disk).
Samsung and SGS are reportedly working on that as well. Samsung apparently produced samples of a 64 Mbit chip in 2004.
I never knew it had been used for digital-data storage; but the device you're describing sounds virtually identical to a regular old "reverb tank" as used in older guitar amps!
....and I'll bet you could use one of those tanks as-is, umodified, for data storage. Not sure what the BW of the end-transducers is; but it's got to be in the khz range.
So many nutty things to play with....so little time....sigh.... :)
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