Hi,
I have two clock domains in my Verilog design (Spartan2), 33 MHz and 20 MHz. My problem: data transport between domains create deadlock. (When I use the same clock in all domains, this send/receive primitive works fine, but I need different clocks...) Can somebody help me? URL, FAQ, RTFM? :)
Thanks, BB
// send @ 33 MHz data_reg = 4; data_ready
I don't exactly know what you want to do but maybe this could be helpful. Read this: At
Patrik Eriksson
MHz.
Your circuit is (approximately) Weinstein's Flancter. Read the details in this URL:
A couple of questions:
1) did you remember to initialise data_ready and last_data_ready?2) did you stop the 33MHz side from sending, by having it look at the value of last_data_ready? If you send two values, then data_ready will toggle twice and the 20MHz side will not see it.
HTH
-- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.