Hi, If you have strong verification skills and have used a language such as SystemVerilog, e, Vera, or SystemC for verification and would like to be able to use VHDL, you should be participating in the Accellera VHDL enhancments effort.
Some of the tasks on our list are adding OO, interfaces, constrained random, functional coverage, verification data structures, ...
You do not need to be an Accellera member to participate. Go to the webpage
Under join here, select the appropriate "click here" link (Accellera member vs. non-member).
Non-Accellera members fill in your name and information and send the request to Lynn Horobin, Administration & Marketing. In the big text box, ask to join Accellera VHDL TSC, VHDL Extensions subcommittee, and VHDL Requirements subcommittee.
Note that most decisions are made by consensus of all participants. Only contentious items are decided by a member based vote. In the last revision, I think there were only 3 of over 100 items resolved this way.
Of course for those of you who belong to companies with sufficient resources, membership in Accellera will help fund the effort (mainly LRM editing task) and is greatly appreciated.
Best Regards, Jim Lewis VHDL and VHDL Standards Evangalist