BCD to bin convertor

Since BCD to Bin is the easy direction (a bunch of adders), why is it you don't care to try it yourself? Are you limited by speed? Latency? Resources? CPLD rather than FPGA implementation? How many digits do you need?

in

(probably just enough to get his homework done) l;-)

It's a matter of time. I have a lot to do inside this FPGA and outside it on the board. I'am more aware about board design than FPGA. So if I can have this part or some clues to begin quickly, It's welcome. I have no speed or resource constrain, and I will use a Spartan FPGA.

Thank you

"John_H" a écrit dans le message de news:aAZbd.33$ snipped-for-privacy@news-west.eli.net...

I have stoped doing homework 12 years ago.

"Rich Webb" a écrit dans le message de news: snipped-for-privacy@4ax.com...

why not just type it in..... case n is when '4' => bin It's a matter of time. I have a lot to do inside this FPGA and outside it on

you

possible

You don't say if it is to be fully combinatorial or if it can use multiple clock cycles. A combinatorial approach requires 10 adders, not all of 16 bits. If you can use mulitple clock cycles, the amount of logic can be greatly reduced. Here is a clocked version that requires N+1 clock cycles to produce a result. I will let you add the multiplexor at the input if needed as well as the control logic to count to five. This can also be shortened to N clock cycles if needed.

slvxx is a subtype of std_logic_vector of range xx-1 downto 0.

signal bin_value : slv16; -- output binary value signal digit : slv4; -- input decimal digit signal start : std_logic; -- reset the counter to zero to start signal load_digit : std_logic; -- add the next digit into the register

process (clk, reset) begin if (reset = '1') then bin_value '0'); elsif (rising_edge(clk)) then if (start = '1') then bin_value '0'); elsif (load_digit = '1') then bin_value