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Aurora sample design: Testing/Eye Diagrams

Hi All,

I have the following issues while trying to test a sample Aurora core. I generated a core w/ the following specs: HDL: Verilog, Lane: 1, Lane Width: 2, Interface: Streaming, Upper MGT Clock: BREF_CLK, Upper MGT clock on GT_X0Y1 (from ucf file, corresponds to MGT4 for a ML321 board)

After using xilperl to compile the design files, I simulated it using Modelsim, and uploaded the bit file using Impact to the board.

I'm trying to test the core by feeding a 3.125Gbps (default data rate based on onboard oscillator) PRBS signal onto MGT4(RXP & RXN). I test the output signal from MGT4(TXP & TXN) by connecting it(TX ports)to a oscilloscope and/or spectrum analyzer. Ideally, you would expect the protocol to simply transmit that data that it received at the RX ports, but the protocol fails to do that. I get an extremely weak signal on the spectrum analyzer and bad eye on the scope. I also tried feeding in a clock signal of 50MHz into BREF_CLK and testing the setup w/ 1Gbps PRBS signal, but that didnt work either.

Can you tell me where I might be going wrong?

Thanks, Billu

Reply to
billu
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For starters the Aurora core implements the Aurora Protocol so feeding the receiver a raw PRBS pattern is seen as garbage as it doesn't match the protocol.

You didn't mention what other logic you wrapped around the core to source and sink the Local Link TX/RX interfaces. If you left these unconnected in your design, then it's likely that almost everything has been trimmed.

However you are getting something out of the TX pair so the bitstream is doing something (probably constantly sending the initialization portion of the protocol since it never gets a receiver lock). Since you are getting a bad eye on the scope I would suggest checking your scopes termination setting and set them to 50 ohm with AC coupling.

You are using the ML321 and these boards are shipped with pre-compiled BERT designs on the SystemACE CompactFlash card. Have you tried just using these designs for your initial testing?

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Thx for your response. I already did some initial testing using the pre-compiled BERT designs that came with the board. I'm trying to take a step ahead by playing around w/ the Aurora core, b/c I need to work with other protocols like PCIe (PCIe core) and flow control in the future.

The reason I tried to feed a PRBS pattern into the MGT's is b/c thats what the BERT design used as a sample datastream. So, I'm guessing its not possible to use a datastream out of a external Pattern generator to test the Aurora design using the setup that I talked about. Is there a sample code available to create a stimulus signal to test the core using this setup. (Someone had suggested that I implement a counter and use that as input to the core. I'm still having some trouble w/ that b/c I'm still in the process of learning HDL and I'm not sure how to link that up w/ the Aurora core)

I'm not sure if I understand your question about other logic being wrapped around the core to source and sink the Local link interface.(pardon me.. still a novice at FPGA design, HDL) . I just setup the core, compiled the design using xilperl and uploaded the bit file using IMPACT.

I just made sure that the scope's termination setting is 50 ohm with AC coupling, so I'm not sure if thats the issue. The signal in the spectrum analyzer itself was too weak compared to the input signal. I'm in the process of veryfing this, but I think I'm getting the same output on spectrum analyzer when I feed the PRBS signal on MGT9 RX and check the output from MGT9 TX (even though sample design has been configured on MGT4)

The other th> billu wrote:

Reply to
billu

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