Which MCU has these features?

Ghazan Haider said

This isn't any of the micros you named, but take a look anyway:

I'm not connected with the company and I've never used it - just looks like an interesting option.

Casey

Look at Intel's XScale variants, they have stacked die solutions that have more than you ask for. TI was talking about a similar thing and may have that in their OMAP line.

-jg

Ghazan Haider wrote: : The linux-tiny project has reduced the linux kernel down to ~300kb, : able to run in 2MB of RAM. With uclibc and busyboy, I can have a : running system in under 2MB of flash.

: Is there a dragonball, ppc, mips or sh3-based chip out there with both : 2MB RAM and 2MB flash onboard?

Only as an "Multi Chip Module (MCM)" in the form factor of a BGA:

But then again, Axis has already ported Linux onto this module and they are shipping products (I.e. Networked cameras) with it...

I've been aiming for low-cost and low-power. If the cost and power are low enough its acceptable (given of course no glue-logic required). I'd also underclock the system for lower power. The intention is to run the system on solar power like larger calculators.

I should've also mentioned an LCD interface is preferred, although I could with enough IO pins implement that, so there should be a minimum of 8 pins for the LCD.

DIP, BGP, all acceptable, and in fact a smaller size will also be preferrable, but with all these aside, is there any MCU that runs either linux or netbsd with 2MB R/2MB F ?

Not on a single die. A micro core like ARM, MIPS, etc requires several metal layers on top of the chip (interconnects) due to its complexity. A flash or RAM array is a flat 2D array of cells which does not require the extra metal layers. When you put both memory and CPU on a single die, you save on bonding and packaging costs. But on the other hand the memory section of the die is much more costly (in dollars per mm2) than it would be if manufactured separately, because it had to go through those extra process steps even though they weren't laying anything down in those areas. As the size of the memory area grows, a break-even point is approached. I'm told that the break-even point is between 512K and 1M.

So it is not cost-effective (external chip vs. on-die memory) to make large memories on the same die as the processor. Once you cross-the break-even point mentioned above, the only options are stacked modules or side-by-side hybrids. These devices are undesirable due to poor vibration resistance and EMI issues.

How long have you wondered if you were told that the break even point is between 512k and 1m?

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Not so much worried about cost as power. I'm hoping more for 90nm process-ARMs, and the reduced power with the ram and flash onboard. Space isnt an issue either.

Your comments however made this issue very clear to me. Thanks.

You might not be, but the chip vendors are! Unless there are special app-specific constraints, they won't make an integrated device that is more expensive than multidie solutions...