ATmega SPI question

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Hi all,

Supposing AVR is a configured as a Master SPI device.
Is it possible to discard AVR master SCK output signal and make SCK as an
input in order to apply external bitstream clock.

My app is connecting a Quad voice A/MU law Codec (MSM7705) to an AVR SPI
bus.

Many thanks

Re: ATmega SPI question

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Probably not -- why can't you configure the SPI port as a slave to get
your job done?

--

Tim Wescott
Wescott Design Services
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Re: ATmega SPI question
Le Mon, 14 Mar 2005 09:07:59 -0800, Tim Wescott a écrit :

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Hi Tim,

Configuring SPI bus in slave mode may require one more signal to drive SS.
AVR received and send at the same time DOUT and DIN to and from CoDeC.
Master SPI does not require SS driven, IHMO Master mode should be more
simple if fortunenately SCK would  be a real clock input.

Habib,
betula.fr

Re: ATmega SPI question
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But, by being master, the SPI interface knows exactly when a byte starts,
because the transmission is started when a byte is written in the data
register. In slave mode, you only know the beginning of a byte by detecting
the assertion of SS. In short: what you want is impossible.

Meindert



Re: ATmega SPI question
After reviewing:
http://www2.okisemi.com/site/datasheets/msm7705-01-02-03.pdf?var_docid=msm7705-01-02-03&var_intro=Intro-3480

This can be done with a simple CPLD.
( did it once already, albet 2 years ago )

Make the AVR an SPI master, with the 7705 a slave. The CPLD will
translate the RSYNC into a "start". Count 24 BCLK pulses into 3 SPI
bytes. After the first SPI interrupt, wait for the other 2 bytes.

No Problem.


Meindert Sprang wrote:
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Re: ATmega SPI question
Le Mon, 14 Mar 2005 20:21:22 +0100, Meindert Sprang a écrit :

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Hi Meindert,

Take a look at this :
http://cjoint.com/?dpjsxvXDQV
AVR is configured as a slave. SS is grounded, therefore AVR is not able to
update SPI shift reg for transmit after a byte is completely received
from CodeC. That's why i'm seeking about Master SPI mode with AVR.
Believe me i'm not a flasher !

Habib
betula.fr


Re: ATmega SPI question
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So your problem is SS stays low, you cannot access the shift register. Can't
you connect SS to the same sync signal that you feed to RSYNC?

Meindert



Re: ATmega SPI question
Le Tue, 15 Mar 2005 09:42:52 +0100, Meindert Sprang a écrit :

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Rrrrrriiiiiiiight !
 you cannot access the shift register. Can't
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I cannot do that regarding FSYNC waveform. It seems that a little more
complex signals generation circuitry must be implemented to drive SS
properly.

Many thanks, Habib
betula.fr


Re: ATmega SPI question
Le Tue, 15 Mar 2005 10:11:06 +0100, Meindert Sprang a écrit :

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SS controlled by soft, AVR as a Master ... it could work, but i will try
to find out more about AVR Slave mode. In fact i'm not very inclined for
the moment to cut PCB traces and so ... for implement AVR Master mode.

For sure anyway it will work this very day.

thanx, Habib
betula.fr

Re: ATmega SPI question
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Mmm, you would have to cut SS anyway if you want to run the AVR in slave
mode, to be able to read and write to the SPI shift register.

Meindert



Re: ATmega SPI question

[...]
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Hello Habib,

I use the Mega16 as a slave on an SPI line. And there is no problem to
transmit more than 8 bit when /SS stays pemanently low. When the 8th
bit is transmitted, MCU will receive a SPI interrupt (if this interrupt
is enabled), no matter what logic state /SS has. The only problem is
that you have only about half a SPI-clock cycle of time for writing the
next transmit data byte into the transmitter register.

Hope that helps.
--
****----*-------*-------*-------*-------*-------*-------*-------*----****
*\ Viele     --         Volker Bosch                                 \***
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Re: ATmega SPI question
Le Tue, 15 Mar 2005 19:45:56 +0100, Volker Bosch a écrit :

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Hi Volker,

I'm quite puzzled. SPI may be reloaded by AVR as Slave device regardless
~SS level ?

here a code snippet i tried :

#include <io.h>
#include <interrupt.h>
#include <signal.h>
#include <pgmspace.h>

#include "init.h"
#include "types.h"
#include "uart.h"
#include "maya.h"
#include "pcm.h"

u08 pcm_in[256];
u08 pcm_out[256];
u08 spi_release = 0;

/************************
 * SPI Interrupt handler
 ************************/
SIGNAL (SIG_SPI)
{
  static u08 i = 0;

  /* Read before Write SPDR !!! */
  pcm_out[i] = SPDR;
  SPDR = pcm_in[i++];
  
  if (i == 254)
    spi_release = 1;
  if (i == 255)
    i = 0;
}

AVR as a slave, SPDR never been updated in that code. In fact, the same
byte received by the slave (MOSI) is transmitted the next shift process
into MISO pin.

Habib
betula.fr


Re: ATmega SPI question
Hello Habib,


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Yes. But you have to write the first data byte into the transmit register
`by hand' before you enable the SPI interface. When /SS is pulled low, the
data byte in the transmit register is shifted out (Beware: no SPI
interrupt is triggered when /SS is pulled low!). When the last bit of the 1st
byte is shifted out, the first SPI interrupt is executed by the MCU. The
irpt-handler has to read the 1st received byte from the receive register
and write the 2nd byte to be transmitted into the transmit register.

--
****----*-------*-------*-------*-------*-------*-------*-------*----****
*\ Viele     --         Volker Bosch                                 \***
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Re: ATmega SPI question
Le Wed, 16 Mar 2005 20:33:01 +0100, Volker Bosch a écrit :

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Hi Volker !

Many many thanks for your blessed relief !
SPI comm between AVR and MSM7705 CoDec now works with AVR as a slave. You
're right for timming shift reg updating (1/2 MCU clock phase)

Thankx, Habib
betula.fr

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