Analyzing a circuit

AoE Chapter 3 - circuit ideas A (high-input-impedance follower)

Also here:

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and at the end of the post.

1) How do you go about analyzing this circuit? how do you approach it? I ca n do the DC analysis fine but the AC analysis is a bit difficult.

My approach was to assume all caps are shorts then assume a voltage wiggle at n007 (where R4 and R5 meet) and then try to calculate the currents. I ca n figure out most of the currents but it's hard for me to figure out what d rives the changes in the BJT collector current, given that the base and emi tter sorta move in sync. Of course I can't really understand why the circui t behaves the way it does, but simulation confirms that the input current i s incredibly small. It appears that the difference between emitter/collecto r current and the current in the emitter resistor that ends up being really small.

2) How would the circuit designer arrive at such a circuit? Just plain inge nuity or are there specific building blocks?

I appreciate the insights, I'm trying really hard to get better at analyzin g transistor circuits and I understand the basics of transistors but can't pull this off.

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SYMBOL cap 128 16 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C2

SYMBOL cap -336 96 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C3 SYMATTR Value 1000p SYMBOL res 48 256 R0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL voltage 544 -160 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 9 SYMBOL voltage -416 128 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value SINE(0 1m 1meg) TEXT -450 424 Left 2 !.tran 20u

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Reply to
M. Hamed
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I would saty a circuit designer would not be likly to ever design that circ uit. but that's OK.

First of all, what is the goal of that circuit ? I see I guess a usable amp lifier but with maybe some strange charactrostics.

The emitter of Q1 dominates via those caps, but where it is going has littl e apparent effect. Changing the drain voltage of J1 is not going to vary th e current much. The other cap off off emittter of Q1 is working into a seri ously high value resistor so it will have a very limited effect.

Further, at queiscence, Q1 should be biased at half the supply voltage but that is impossible because R1 and R6 are bothe 10K. the base of Q1 will onl y go to half the Vcc when J1 in in saturation.

Now for the AC, that does say 1 mHz rigght ? So we can forget aout Xc here. C2 going to the drain of J1 is going to have so minimal effect it can be d isregarded. When you run devices in linear mode, usually a change in overal l voltage doesn't cause the increase in current you would see in a resistor for example. Thinking the signal from the drain of J1 would affect the out put somehow into a 1 K from a 10 K - ain't happenin. Now IF you were taking the output from the collector of Q1 that would be different. If you look a t the deflection amps in CRO scopes you can see that type of shit it action .

But bear in mind these guys took about a year to design a board over at Tek tronix n shit. I shit you not. That is why their shit cost more than a new car.

But your circuit looks smokeproof ! That is good. Now simulate some audio i nto it and see how it reacts. Then we'll go over to Audiokarma. 'Them peopl e love shit like this, and some of them have that mad scientist gene.

Reply to
jurb6006

Nowadays, you can just Spice it.

If you want to do it analytically (and approximately) the jfet is a follower that has unity gain and an output impedance that is 1/gm, where gm is the fet transconductance.

That is loaded by 10K and the base of the NPN. The NPN input impedance is about 1K * beta. So the fet gain, loaded, is a bit below 1.

The NPN emitter follower has an output impedance of about 25/Ie, with Ie in mA. That makes another voltage divider wih its load, 1K||10K. So its gain is a bit below 1.

The two bootstraps increase the input impedance and the non-ideal voltage gain of the jfet.

It's hard to say where circuit ideas come from. Most circuits combine a lot of previous practice with a bit of inspiration. You learn a lot by studying existing circuits (in books, manuals, whatever) and also studying component behavior. This circuit uses two common ideas, voltage followers and bootstrapping.

I have a mental process that sort of consists of taking a pile of candidate parts, throwing them up in the air, and seeing how they land... essentially designing random circuits. The number of such circuits that you can make from, say, 10 parts is literally astronomical. But a trained and open brain can parallel-process evaluate that astronomical number of possible circuits. Experience with existing circuits and a mental ability to "see" how circuits work helps the brain to sort out the few reasonable circuits. So, keep trying things and analyzing circuits to train your instincts.

A pad of blue-grid paper is invaluable. Evolving a simple circuit might burn up a couple dozen sheets of failed attempts.

"Design" is a mental process that is under-studied.

--

John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Win Hill designed it.

High input impedance, low output impedance, gain close to 1.

Bootstrapping the jfet drain increses its AC gain, closer to unity, and decreases its input capacitance.

It bootstraps R5 and increases the AC input impedance.

Win didn't specify the supply voltage, and 9 is too low, at least with

10K as R1. Higher supply or lower R1 is needed to get some voltage across the jfet. Try 15 volts and 5K.
--

John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

That's why I said what I said. This circuit would not be put into use, it i s just for study. And FET needs no bootstrap because its input resistance i s already so high. Actually, thopugh it would probably not be the right way to do it, that circuit could maybe reduce the effective input capacitance. (???) That is pretty much the only useful thing I see.

Actually it as commendable just to ge ta circuit that doesn't smoke. A viab le curcuit I guess would be the word.

Oh, and about the gain being

Reply to
jurb6006

Yes, but not by much. it's working through a 10 meg.

Reply to
jurb6006

C2 makes the AC drain voltage almost track the gate voltage. That reduces the effective Cgd a lot, roughly 10:1 maybe. Cgs is already bootstrapped by the fact that the jfet is a follower. So both Cgd and Cgs appear to be much lower than the datasheet values.

The other bootstrap, C1 through R5, increases the effective value of R5, as seen by the input signal.

--

John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Win Hill puts those example circuits into AoE to encourage people to think.

Bootstrapped jfets are commonly used in low-level circuits, like photodiode amplifiers, to simultaneously increase follower gain and reduce input capacitance.

This has some good theory and examples:

formatting link

--

John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

It can be way better than that, as good as 500:1 or 1000:1, in real life, at least up to a few megahertz. (Happy customers attest to this--bootstrapped bootstraps rock.) The 2N4416 is far inferior to the BF862 for that sort of thing, but of course there weren't any BF862s in

1989, when AoE II came out.

You do have to use a good quality current sink load for the JFET, though, because otherwise its voltage gain can be quite a bit less than 1.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Only if you are a bootstrap maniac. I mean that in a good way.

(Happy customers attest to

Win's circuit, with sensible DC biasing, runs around 0.9 overall gain, so the jfet caps are bootstrapped roughly 10:1.

You showed me this trick:

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Of course, the base resistor loads the jfet source, so the bootstrap ratio can't hit truly maniacal levels.

As long as we're here, in the Basics group, allow me to say

DON'T RUN JFETS WITH VDS OVER 5 VOLTS.

or you'll see a bunch of unexpected gate current.

--

John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

A BF862 has a source resistance of about 30 ohms. With a PNP wraparound on the FET (that's shunt feedback, like the classic circuit for current-boosting a regulator, as in the LM7805 datasheet) you can get that down to an ohm or so, in which case the bootstrap's base resistor isn't too much of a problem. You do have to work at making the whole foofaraw not oscillate. ;)

Roight. BF862s like 2 to 3 volts--in that range they pretty well have their full bandwidth, and gate current is a picoamp or two.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

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