1. Home
  2. Electronics Design
  3. Transmission Gate FF

Transmission Gate FF

The TI SN74HCS72 has a diagram showing the internal transmission gate struc ture and I must be misinterpreting how it works. The device is negative ed ge triggered but the logic seems to me to be positive edge sensitive.

For negative edge triggering, the first set of transmission gates should be accepting input through the gates when the clock is high. The second FF i s set to hold it's present value. When the clock drops the first FF holds it's value while the second FF opens and flow that value to the output.

Here's the diagram. Tell me this isn't positive edge triggered! Maybe the reused a diagram from some other document since most FFs are positive edge triggered.

formatting link
gramId=SCLS801

Full data sheet here.

formatting link 

--

  Rick C. 

  - Get 1,000 miles of free Supercharging 
  - Tesla referral code - https://ts.la/richard11209
Reply to
Ricky C
Loading thread data ...

/C is the same as input clock

(1)the gates at the input and also the feedback loop at the output are active if it's high.

(2)When it goes low, the input gets disconnected and the first stage fb loop runs. this gets also routed to the output at the same time. (this is the negative edge trigger)

(1)When it goes back up, the slave loop at the output will hold the value.

Reply to
Johann Klammer

ucture and I must be misinterpreting how it works. The device is negative edge triggered but the logic seems to me to be positive edge sensitive.

be accepting input through the gates when the clock is high. The second FF is set to hold it's present value. When the clock drops the first FF hold s it's value while the second FF opens and flow that value to the output.

he reused a diagram from some other document since most FFs are positive ed ge triggered.

iagramId=SCLS801

Looks right to me: External CLK/ is tied to internal C/. C/ goes to the gat e of the D input NFET; C goes to the PFET. So, CLK/ high enables the CMOS s witch.

-Mark

Reply to
Mark

tructure and I must be misinterpreting how it works. The device is negativ e edge triggered but the logic seems to me to be positive edge sensitive.

d be accepting input through the gates when the clock is high. The second FF is set to hold it's present value. When the clock drops the first FF ho lds it's value while the second FF opens and flow that value to the output.

the reused a diagram from some other document since most FFs are positive edge triggered.

&diagramId=SCLS801
.

Ok, I was missing the fact that the /C was the same as the external clock. Even when it is negative edge, to me it's just the clock rather than clock not.

Thanks.

--

  Rick C. 

  + Get 1,000 miles of free Supercharging 
  + Tesla referral code - https://ts.la/richard11209
Reply to
Ricky C

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.