i don't understand some definitions about SDRAM:
1)COLUMN: smallest unit data....if SDRAM is 4Mx16(=1megx16x4banks), is 16 colum's number of bits or data out bits?Column's number of bits and data out pins are always the same or can differ each other? 2)BANK: in datasheet i found 1,2,4,etc...are these bytes or cells? For example, if bank=2, i obtain 2*16=32bit or 2*8=16bit? Thanks
It would be a good idea to identify the SDRAM that is troubling you.
My expectation would be that a 4Mx16 SDRAM would offer 4M of 16-bit words, which implies a 16-bit parallel data output.
Addressing 4M of data requires a 22-bit word. This could be presented to the chip at 22 different address data input pins, but address lines are often multuplexed; you could use 11 -bit to select a particular row of data out of 2048 columns, then latch this high-order address data and use the same 11 input pins to select particular row out of
2048, thus selecting the particlar word a the intersection of the selelcted row and column. In principle you need a 12th input pin to distinguish between rows and columns, but it isn't always possible to identify a specific pin that makes this distinction.If the data sheet talks about banks of data, it could be that the address is being read in in three steps into 8 address pins, first you select one bank, then one column and finally one row to pick out a particular word. In principle you then have to devote a nineth and tenth pin to distinguishing the bank address from the column address from the row address, but this doesn't have to be the way it is done.
-- Bill Sloman, Nijmegen
Thanks for the help
Ok, but i don't understand how many bit can i obtain from a single address: for example, if i use an 4Mx16 memory, with a single address, i obtain a 16bit data?Single cell is 16bit wide?
Pardon, i have made a big error: what i mean is BURST, not BANK (excuse me)....I've found Burst length=1,2,4,ecc :These values are bytes (Burst_length=2=>2*8=16 bit) or number of cells (2*16=32)?
Thanks
A DRAM is a two dimensional grid of cells, optionally partitioned into multiple banks. In order to read/write data, you first have to "open" a specific row, which is relatively slow. Once the row has been opened, you select which columns (bits) to read/write for that row.
The width of the data bus determines how many columns are read/written at a time. The selected columns are aligned to a multiple of this width. E.g. for a 16-bit DRAM, a column address of zero connects columns 0-15 to the data pins, a column address of one connects columns 16-31, etc.
The rows are divided into banks.
If the DRAM has multiple banks, each bank can have a row open, and you can interleave commands between banks. E.g. issue a command to one bank to open a specific row, then immediately start a burst transfer for the currently-open row on a second bank. By the time the transfer has completed, the first bank's row will have been opened.
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