Does this make any sense?
It solves the drain resistor problem by battling two fets against one another.
Two relays could switch four different gate resistor values, which might help separate gate current noise from resistor Johnson noise.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
I suspect it'll just be a JFET mismatch indicator, with the output riding against whichever transistor is hotter.
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Well, you'd have to close two feedback loops to set the operating current for both fets.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
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Are those JFETs then intended to be a complementary pair? Cancelling... each other out? Is one a known reference?
I think you might be mainly testing the noise in R3.
-- Les Cargill
I'm not quite making sense of something. If the feed to the LEDs isn't twea ked to get the fet pair's output to 0v, the opamp gain will vary depending on its diode conduction. That's no good. If the feed to the LEDs is tweaked to get the fet pair's output to 0v, the opamp has no need for its feedback diodes.
NT
What are the photodiodes for?
I think it measures power supply noise best of all, you'd need a lot of decoupling. As drawn there are two supply rails to silence, single supply may be easier.
Just what is this drain resistor problem? Why not just replace your Q1 with a resistor for Q2s drain load?
piglet
A little bit, but I have to guess at what you are trying to do.
Do the two PD's see the same light source... trying to get rid of noise in the light source? I then think you are mostly going to see the shot noise of each PD. No?
If are trying to do some sort of correlation thing.. Then I'd want each jFet to see the same current... from the same PD. Then subtracting the signals would leave only the jfet noise... I think.
Is that what you are trying to do?
George H.
No, they are two of the same part.
As a practical matter, probably not. The nice thing about this circuit is that there is no fet drain current in R3, no DC current at all, so it can be big. Gain is linear on R3 but Johnson noise is square root.
Maybe the diodes could go, to allow a bigger R3 and more noise voltage output. Maybe some higher voltage clamp.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
There would have to be two servo loops to tweak net drain current, and to exactly balance the two currents. That can be done with a few opamps.
The diodes were intended to tame things during startup, but they do limit noise swing so maybe aren't a good idea. They aren't necessary.
Hey, I drew that in about 20 seconds. It might need a little work.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Isolated, low noise gate drives, so we can servo the two gate currents as needed.
They are photovoltaics. Handy sometimes.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Sure, it needs super-quiet supplies.
The resistor value would need to be low to make the DC circuit work, and it would have to change if the tests covered a wide current range. Johnson noise becomes a issue.
If the fets run constant-current, power supply noise matters a bit less, too.
Jfets get weird above a few volts s-d, so the supply voltages will be low, but the fets will still be sorta into their constant-current zones.
I was just background thinking about Phil's jfet test issue, and thought this idea might work.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
The pd's are just quiet gate drive isolators. Their shot noise is zapped by the capacitors.
The opto input currents have to be individually servo'd to set the desired fet operating current, and also balance the currents to get zero DC at the output of U1, so all we see there is the fet noise.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Jfet_Tester_1.JPG
If you have a dewar of LN2 around you could hang the gate resistors an inch or so below the board and chill them to 77K. Compare the results with the noise at room temperature to get the resistor noise. Insulate the board with a thin layer of styrofoam.
If thermal noise is significant enough to matter you could probably just compare room temperature with dry ice in an acetone bath -- that's a bit over a 3:2 difference in absolute temperature right there, which should lead to a quite measurable drop in noise -- but the styrofoam would get problematical.
Or, inject a known voltage into the gates to get the gain, then use the known relation between temperature and thermal noise to work out what it is and discount it.
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I figure that the gross fet specs are known, or can be measured, so this rig can assume all that. All we really need to know is Gm, since the load is a summing point.
Actually, we know the gate resistor Johnson noise too, so we don't need to do tricks with switching resistors. But if the gate current noise is much less than the resistor Ej, we have a problem.
RF folks like to measure NF by adding noise to the input of an amp and noting the change at the output. But if you know the gain, you can do absolute output noise measurement and work from that.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Am 01.08.2016 um 18:01 schrieb John Larkin:
But the gain of U1 would depend on the source impedance of Q1 Q2 and that is hard to determine. Also, Q1 is a follower and Q2 common source with different gains for their respective noise.
I did a preamp with 20 averaged ADA4898 op amps. The input noise density is abt. 220 pV/sqrt Hz, so the noise of a 60 Ohm resistor at the input clearly dominates and you can use that as a 1 nV/sqrt Hz calibration line on the spectrum analyzer. No need to even know the absolute gain.
Currently I try to get the same performance from a bunch of paralleled IF3602. The input bias resistor can then be 100 Meg instead of 10K and I don't need an insanely large input coupling capacitor. 10 uF foil would be enough.
Note that the cap' Z must be less than , say 4 Ohms to shunt the noise of the bias resistor through the low input source resistance, otherwise you do not see the true 1/f noise of the amplifier itself but something that looks like GR noise and is much worse at the low frequency end. (at least for voltage noise)
100Meg may have more voltage noise than 10K, but it is much more easily shorted.So the cap must be much larger than dictated by the low 3 dB corner. I have bought some 5mF wet slug tantalums for the ADA4898 amplifier, that hurts financially and they are polarized. I could not see more noise when I used good Al electrolytics and not even vibration sensitivity, but YMMV, especially if your signal rides on a large DC.
I have also used Vishay VO1263AB optos for bias generation in the FET case: 2 antiparallel photo diodes, one LED with a settable bias current, the other LED in the drain. That really nailed the bias current to one point, ultra-precisely. No matter what or how many FETs. Got the idea from Scott Wurcer from AD.
I finally replaced that by an op amp integrator because I wanted more drain current for my flock of IF3602s than the VO1263 allowed abs max.
Has anybody seen Fred Bartoli recently? He has played with IF3602s also, some years ago.
regards, Gerhard
The transimpedance gain of U1 is R3. The idea is to measure the drain current noise.
Q1 is not a follower. The two fet circuits are each an isolated
2-terminal thing, and they are in series, and are symmetrical.The fets see a summing point, so their source impedance doesn't matter, except for the Johnson noise contribution, so just roll that in.
You could also apply a known-amplitude sine wave to the amp input and calibrate the gain.
A zillion BF862s in parallel would make an interesting amp. They are around 0.8 nV/rthz each.
Polymer aluminum caps are nice. The loop might get slow.
Antiparallel on PV optos is a good idea. You could get +-lots of volts.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Am 01.08.2016 um 21:52 schrieb John Larkin:
Oh, yes. I was somehow fixated on voltage mode.
Did that, ok, only 16 pcs. Was not enough. Maybe i use some more when I have a real board. Dead-bug-wise that was my soldering limit. Would be cheaper & less capacitance than Interfet.
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