does this make sense?

Looks to me the authors are just bloviating. They didn't measure anything! Really, every chip along the bus is a 50 Ohm load? Nah.

Jeroen Belleman

On a sunny day (Fri, 25 Mar 2022 12:57:23 -0700) it happened John Larkin <jlarkin@highland_atwork_technology.com> wrote in snipped-for-privacy@4ax.com:

Dunno, had to think about that I can imagine the chips form a capacitor and the traces the inductor. That gives you a transmision line that *probably* would preserve the form of a fast pulse?

Not sure that is what they are saying, Chip input capacitances have tolerances L L L -----------trace---- trace------------trace---- [] fast pulse | | | Zin source === === termination | | Cin chip | | /// /// /// /// chip chip

The chips are close together, but not close enough to be lumped capacitances. The guy is talking about memory chips with differential signals. The traces are almost certainly terminated as shown in the initial analysis, at each chip. The aggregate effect of the combined terminations is -15 dB of attenuation. At first I thought this had to be wrong, but then I realized the differential signalling can work properly with very small signals at the receivers. If the graphs are in volts, the differential signals seem to swing between 0.6V and 0.7V.

The guy very clearly says he used an EM solver to start. That's because the signalling on a DRAM card is not impedance controlled because of the distributed input capacitances. The EM solver provides the S parameters and the "Keysight ADS" produces the eye diagrams. They mention the Keysight ADS multiple times, so obviously these are employees of Keysight and are promoting the product. That's why the step of analyzing the output of the EM field solver is not described in much details, not unlike, "and then magic happens".

Sure, a txline can be analyzed as a string of LCs... lots of them [1].

But 50 ohms DC at every dram chip?

On a sunny day (Sat, 26 Mar 2022 10:01:34 -0700) it happened snipped-for-privacy@highlandsniptechnology.com wrote in snipped-for-privacy@4ax.com:

The author writes he uses 50 Ohms just for ease of simulation or something.

Reading it again I think they do not understand transmission lines :-)

Way to complicated story.

Seems there are only 5 chips per driver... If pure capacitive what losses would there be? I could be wrong, but I only needed above few lines to explain that sort of setup.

The fast DDR controllers run a calibration at startup to tweak out txline skews. They couldn't work otherwise. The DDR controller block in many FPGAs will do that for you.