jfet noise test

Hmm, makes things harder for yourself though -- the PVs have modest gain, but the JFETs don't have feedback, so you have two integrators in the loop. Save a pole and just bias the top one straightaway:

And I filled in the bottom servo (just because). This makes it obvious(?) that feedback (to reduce noise) is an option. Maybe you'd use R3-C2 when JFET self-noise is low enough, or close the loop without filtering (oh, and obviously, compensation not shown..) to do as good as whatever IC1B can offer (which might not be an op-amp itself, but using a low noise BJT, which would be acceptable given that R5 will be a moderately small value, say 1k or less).

Tim

That works, but there's a conflict with Bottom_Bias driving the opamp output. Just eliminate Bottom_Bias.

Vref may as well be zero. So it runs with the source-drain node at ground.

Well, it wouldn't be an input anymore, just an "info" output.

Or, you don't even really care what it is, anymore, as long as the amp is taking care of things.

Ground makes a fine reference. :-)

Hey, just throwing ideas out there... it's a five minute sketch. ;-)

Tim