Maybe it's some models that don't conserve charge, perhaps as they switch regions of piecewise nonlinearities or some such, trying to emulate device behavior. I sort of doubt that the core simulation engine doesn't conserve charge, at least if you set the time steps to something reasonable.
John
=A0 =A0...Jim Thompson
OK, but the channel charge of the mosfet isn't modeled well.
Like I said, you need to be specialized in simulators to know the nitty gritty. My point is it is accepted that spice doesn't conserve charge.
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But you only converge to the reltol limits. There is always some finite error in such a scheme. OK, maybe it should be stated that spice doesn't perfectly converse charge, but my assumption is if you conserve charge, it is by definition assumed to be perfect.
[snip]
I wish you dork-brains would learn to crop/quote properly... I didn't say the above.
Me suspects that Miso is another one of our great AlwaysWrong technican types, pretending to be an expert.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
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I love to cook with wine Sometimes I even put it in the food
IOW, you are saying that Spice doesn't explicitly ensure conservation of charge over the course of the simulation, so any tolerance error in individual steps will accumulate?
Similar to the way that a naive numerical simulation of d²x/dt² = -kx typically won't conserve amplitude?
IME the problem is more that the model (used in the simulation) is very poor rather then any lacking in the way spice computes things (asserting refinements in spice all along the way). I has been this way for 20 years at least. Of course the model capability is an ever finer approximation of the real thing (If and when updated). YMMV
Actually since very early on (I think v. 2a) spice conserved charge. Both the early Ebers-Moll and later Gummel-Poon bipolar transistor models were based on conserving charge. And these were over 20 years ago.
Then your definition is non physical, as perfect charge conservation is not possible. So wise up and cope.
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Wise up and cope? What an asshole!
That's being awfully severe on a mere digital computer. In addition to the obvious floating-point limits, Spice must do discrete-time-chunk extrapolations if it's not to take forever to get anything done. I'd imagine cases, like a steep curvy rise or fall, where discrete block calcs will miss high or low for a while, and accumulate small charge errors. Setting dt smaller may help, at the annoyance of slow results.
What matters to me is whether Spice can conserve charge to, say, 10's of PPM accuracy over a sim run, and how I'd have to set it up to make it do that.
Some circuits, with a real wide mix of taus, like crystal oscillators in the extreme, really stress the accuracy/user patience tradeoff.
John
Not to change the subject (who, me?) but we just bought a heap of samples of 0805-size integrated passive lowpass filters, TDK and some others, and they are very impressive so far. Some are 3-pole, L-C-L for some reason, and some are more.
John
We're using some of those (don't believer they're TDK) to isolate RF buzz (from frequency hopping) from the power supply on some replacement[*] headphone drivers. They've been known to cause as many problems as they solve. The footprint isn't exactly an 0805 (center ground stripe) so bridging across them can be a problem.
[*] Replacement part required because of ROHS, of course.
The Brat is just now creating the footprint; we'll be careful about the bridging situation. The TDK recommended footprint uses weird outer pads, sort of pointy towards the middle.
Two of our frequency synthesizer boards are leaking strange rf things. An FPGA is clocked at 128 MHz, and we're seeing lines coming out at all sorts of bizarre frequencies, with no obvious numerical relation to any clocks, from around 130 MHz up to a GHz maybe (160.34,
175.89...) They seem to be coming from inside the FPGA, and are dead stable in frequency so aren't analog oscillations. The 0805 filters, right at our output connectors, whack things very nicely. Our max signal frequency is 32 MHz, so they don't affect normal operation.John
Yeesh, Jim, I haven't looked at this newsgroup since roadrunner dropped NNTP support. I've missed the chaos and ignorance... You need to thump some of the empty heads.
Anyway, about charge conservation in circuit simulation: The problem was always with MOSFETs. BJTs and diodes were fine from the original SPICE1 code -- if you start with a q(v) equation and differentiate it to get capacitance, things are surprisingly good. Path integrals work out... The problem was the Meyer model for channel capacitance, used in the MOS level 1, 2, 3 models (and others). The model described the capacitances and did a numerical estimation of charge based on them. This was just plain wrong, since they're trying to estimate, e.g., qg (vd,vg,vs,vb) without an integrable function. A good exposition of the problem and first practical fix was in Ping Yang's 1983 paper.
So, MOS levels 1, 2, 3 are probably still wrong in SPICE -- I haven't looked lately. Any of the more recent models, BSIM3, BSIM4, EKV, PSP, all start with q(v) and differentiate to get the (non-reciprocal) capacitances, so they're more-or-less correctly set up for charge conservation by construction. For transient analysis, even if they get the differentiation wrong, as long as q(v) is correct the model will conserve charge -- if it converges.
For the picky, yes there will be some error on each cycle due to convergence tolerances. If the simulator you're using properly implements truncation error timestep control, the loss will be minimal and controllable by tightening reltol and chgtol. If you're using certain 'gold standard' simulators, you'll probably have trouble unless you're some kind of prescient in figuring the right model switches and options. My simulator does quite well.:)
--Steve
Speaking to and of your self i see.
But my point was you couldn't use spice for high accuracy, such as SCFs, which is why switcap was invented in the first place.
I really don't understand Jim negative comments about me, but trust me, I've delivered silicon. Then again, when it comes to Jim, you have to look at the source and just shrug it off as some jerk.
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Oh, are you telling me your are rubber and I'm glue. Hey, that's really telling me. Oh boy.
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Charge redistribution circuits go through many cycles, so the error can accumulate. Like a said many posts ago, you would see this is cyclic converters.
In the NMOS days (yeah, I'm that old), there was great effort into studying this charge error since you didn't have complimentary switches. Dummy switch schemes were tried in spice and silicon with little correlation.
"complementary" ---
Jeroen Belleman
=A0 =A0 =A0^^^^^^^^^^^^^
OK, you win. ;-)
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