The ones we use are from MuRata (NFL18ST).
When you say it's coming "out of" the FPGA... How? Power? Signal pins? Air? In any case it is weird. Did you ask Xilinx about it?
The filters were making my output driver (LM7171 DSL driver used in a Howland current pump) oscillate at 160MHz and suck gobs of power. Bridging them with a zero ohm resistor eliminated the problem, but as I said, it can be tricky with the ground stripe in the middle.
In situations where the errors can build up badly, e.g. long-duration orbital calculations, there's a tendency for the energy of the system not to be conserved by the usual DE integration methods, e.g. predictor-corrector or Stoer-Bulirsch. Those sorts of calculations are now done using what are called 'symplectic integrators', which inherently conserve energy to the level of roundoff. It's probably quite possible to do the same sort of thing for charge conservation in circuit simulation, but it would seem to be unnecessary, since almost all useful circuits have current flowing in and out of them.
Cheers,
Phil Hobbs
No. SWITCAP is much faster.
I guarantee I've delivered _far_more_ WORKING silicon than you.
You said the simulator didn't conserve charge. You were wrong. I know you have a lot of trouble admitting you're wrong. Get over it, JERK!
...Jim Thompson
We're not really sure how it gets out. The FPGA feeds dacs clocked at
128, which feed lowpass filters, output amps, and the connectors. We're seeing lines as big as -45 dBm coming out the connectors. If you wave a spectrum analyzer probe around the board, the junk is most intense just over the FPGA. Some weird points: the lines are at different frequencies on the two different boards, even though the fpga's are very similar; one board tends to have lines in pairs, a couple of MHz apart; we can almost swear that once we saw the whole spectral forest shift around, in one instant on one board, when nothing else was going on.It would be fun to really investigate the cause of this, but all we have time to do is fix it.
Luckily, we have a 50 ohm resistor between our output amp and the filter+connector.
John
Cheers! Rich
=A0 =A0 ...Jim Thompson
=A0 | =A0 =A0mens =A0 =A0 |
=A0 | =A0 =A0 et =A0 =A0 =A0|
=A0|
=A0 =A0 =A0 |
You certainly deliver more bullshit than I do.
for
one
boundaries
spice.
Your twisted misrepresentations are on you.
Makes me wonder about internal frequency multipliers leaking somehow.
If the frequency multipliers were leaking it would have to be at a multiple of the input clock. John indicated there is no (obvious) numerical relation.
onserve
around
BSIM, for
ate in one
boundaries
or's spice.
ey
to
nps to
ou
nI'm sticking my fingers in my ears and saying "Nah nah nah I can't hear you."
Who constrained the frequency ratios to integer? Not i. Any rational ratio is reasonable. Alternatively there would have to be free running oscillations, with whatever causes they may have. The frequencies were noted for being stable were they not?
The frequencies bear no resemblance to the output either. Do you think there is a random rogue multiplier with an antenna on it? Note that John said there is "no obvious numerical relation to ANY clocks".
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