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June 13, 2008, 1:37 am
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The technique described in the proposal is also known as Wafer Scale
Integration and has been around for at least 20 years. A Wikipedia
article on wafer scale integration can be found at
http://en.wikipedia.org/wiki/Wafer-scale_integration . It states "The
vast majority of the cost of fabrication (typically 30%-50%) is
related to testing and packaging the individual chips. Further cost is
associated with connecting the chips into an integrated system
(usually via a printed circuit board). Wafer-scale integration seeks
to reduce this cost, as well as improve performance, by building
larger chips in a single package 96% in principle, chips as large as a
Of course this is not easy, since given the flaws on the wafers a
single large design printed onto a wafer would almost always not work.
It has been an ongoing goal to develop methods to handle faulty areas
of the wafers through logic, as opposed to sawing them out of the
wafer. Generally, this approach uses a grid pattern of sub-circuits
and "rewires" around the damaged areas using appropriate logic. If the
resulting wafer has enough working sub-circuits, it can be used
This wikipedia article also states "Wafer-scale integration, WSI for
short, is a yet-unused system of building very-large integrated
circuit networks that use an entire silicon wafer to produce a single
"super-chip". Through a combination of large size and reduced
packaging, WSI could lead to dramatically reduced costs for some
systems, notably massively parallel supercomputers."
The following abstract from http://www.springerlink.com/content/xg4r721l1hx =
Alessandro Zorat1, 2
(1) Department of Computer Science, State University of New York at
Stony Brook, 11794 Stony Brook, New York, USA
(2) Present address: Istituto di Ricerca Scientifica e Tecnologica,
Loc. PantE8% di Povo, 38050 Trento, Italy
Received: 25 July 1986
Abstract With the advent of wafer-scale integration (WSI), the
placement of several processors on a single VLSI wafer is becoming a
realistic possibility. To avoid the problems of a very low yield
inherent in any silicon component of (very) large area, redundant
components will be used.
In this article we examine three different solutions for reconnecting
the nonfaulty processors so that the resulting network is a square
grid. We then present results of simulations for various percentages
of faulty processors, which show that a small amount of redundancy is
the interprocessors paths and a simple back-track based algorithm can
produce a resulting grid that, while not necessarily optimal, includes
most of the nonfaulty processors.
This research was supported by the National Science Foundation, under
grants ECS-80-25376 and ECS-83-05195."
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