Is it a lost cause?

PDP11 used 4 X 4 bit TTL register chips to make its 8 X 16 registers.

Reply to
gareth G4SDW GQRP #3339
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The TMS-9900 chip from TI had three 16-bit register internal to the CPU: Program counter (PC), Status register (ST), and Workspace Pointer register (WP).

The Workspace Pointer held a pointer to memory where 32 bytes held what was used as the general purpose registers of the CPU. Changing context involved changing the WP to point to a new register set... among other things.

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Reply to
Charles Richmond

I never dealt with anything bigger than a 1903S when writing PLAN or using the macrogenerator. Later, when I was a G3 system programmer, I don't think I touched code at a lower level than GIN (and usually with a layer or two of macros below anything I got my fingers on), COBOL and Algol68R. I only found out about the hardware registers in the bigger machines fairly recently, but even then I'd guess that there were many less hardware register sets than running programs and that program switching would involve copying the accumulators + pc set between the hardware registers and the program image.

BTW do you know how much of lower program memory was supported by hardware? Was it just the accumulators + PC, or was anything else, e.g. the option switches (word +9?) also put into a hardware register?

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Reply to
Martin Gregorie

Au contraire, sounds like introduced performance.

Reply to
Scott Lurndal

You really have no clue as to the complexity of a modern processor.

Blueprints. Sheesh, give me a netlist instead.

Reply to
Scott Lurndal

Once again you resort to personal abuse.

Shame on you.

Reply to
gareth G4SDW GQRP #3339

As usual, you are incorrect. See the "ADR" and "ADRP" instructions.

Reply to
Scott Lurndal

More personal abuse.

addresses do not give you the ability to write to the PC.

Reply to
gareth G4SDW GQRP #3339

Writing to the PC is what happens in a jump instruction on any processor.

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Rick C
Reply to
rickman

spring soph yr got a 2hr intro to fortran class (1st exposure to computers). that summer I was hired to do re-implementation of 1401 MPIO for 360/30. The univ had 709 with 1401 as unit record front-end for 709 (709 ran tape-to-tape, with tapes manually transferred between 709 and

1401, MPIO was 1401 program that card reader -> tape and tape -> printer/punch). The univ was sold a 360/67 replacement, as interim transition, the 1401 was replaced with 360/30. The 360/30 had 1401 hardware emulation mode ... so could run 1401 MPIO directly. I was hired to implement in 1401 MPIO in native 360 assembler, got to design and implement my own monitor, device drivers, interrupt handler, error recovery, storage management, console interface, etc. Univ. shutdown normal operations at 8am sat until 8am monday ... and I would have the whole datacenter to myself for 48hrs straight. Monitor evanutally was slightly over box (2000) cards ... with conditional assembly for stand-alone mode and running under os/360 with open/close, get/put i/o (stand-alone version took 30mins to assemble, os/360 mode took over hr to assemble, os/360 I/O DCB macros took approx 5mins each to assemble under early OS/360 PCP releases on 360/30).

I got other tasks when school started in the fall, and continued to have

48hr dedicated weekend time (although making monday classes was little hard after 48hrs w/o sleep). The following year, I was hired fulltime responsible for IBM production operating system.
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Reply to
Anne & Lynn Wheeler

The PC is not accessible as though it was one of the general registers as it has been in the past in ARM architectures

Reply to
gareth G4SDW GQRP #3339

You can read and write it. What more do you want?

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Rick C
Reply to
rickman

Computer serendipity where you do such fun things as setting and clearing bits in the PC, or shifting it left and right, and so on.

Reply to
gareth G4SDW GQRP #3339

You can do anything with the PC you want. Your only limitation is yourself.

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Rick C
Reply to
rickman

In *some* PDP-11s....

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Reply to
Bob Eager

But that's what happens in practically *every* register based machine. Except that they're stored in a process control block, usually.

(excepting machines that have two sets - at the low end, the Z80, higher up something like the PDP-11, which had one for each mode)

Just the accumulators, and presumably the PC. I don't actually think it

*was* the PC, it was just somewhere to stash it between times.
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Reply to
Bob Eager

Agreed. Ancient history, while useful for context, has no place in modern teaching.

By the way, all, the OP "gareth" is actually Gareth Alun Evans, of Chippenham, Wiltshire, a notorious troll and convicted criminal who has reduced several previously useful newsgroups, including uk.radio.amateur, to rubble.

You may wish to decide whether it's worth replying to him. Trolls are best ignored, then they wither on the vine and die or go hunting for pastures new. By replying to them, you only feed their need for attention.

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Reply to
Mike Tomlinson

Quite so. Those reading "gareth"'s advice would be well advised that his experience stems from the era of valve-powered equipment and is in no way applicable to modern processors, although he seems unable to recognise this.

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Reply to
Mike Tomlinson

On Tue, 14 Jun 2016 10:54:51 -0000 (UTC), Martin Gregorie declaimed the following:

Sigma task switch was done via an "eXchange Program Status Doubleword", which held the new program counter value, condition codes, and (for expanded machines) an indicator for which bank of registers to activate (apparently one could add multiple 16-register banks to the processor).

No standard stack register -- though one could dedicate a register to do stack operations, the common (FORTRAN/non-recursive) paradigm turned into indirect references via subroutine link register (also not a dedicated register, one specified the link register in the call instruction). Arguments were passed by...

call, data data ...

subroutines would then copy the addresses by indexing off the , ending by incrementing the by the number of arguments.

Sigmas were (in)famous for having something like 224 interrupt vectors (when IBM 360/370 only had 7 and had to poll to determine which device interrupted). Each interrupt vector basically held a program status doubleword, so an exchange PSD made for fast response.

The "big" assembler for them didn't even have a hard-coded instruction set... Programs started with a "system ..." declaration which basically loaded a macro definition file for all the opcodes. Out of boredom one day, I wrote a "system" file that would generate absolute 8080 code. (I forget the instruction format declaration but something like:

MOV S:SIN,2,3,3 x'01',AF(1),AF(2)

"Form an instruction with three fields sized 2-bit, 3-bit, 3-bit using constant x01 for first, argument field 1 for second, argument field 2 for third" (also had LF and CF for label and command field -- presuming one had defined constants for the 8080 registers the above made

MOV H,B

a valid instruction to the assembler))

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	Wulfraed                 Dennis Lee Bieber         AF6VN 
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Reply to
Dennis Lee Bieber

On Tue, 14 Jun 2016 11:05:15 -0000 (UTC), Martin Gregorie declaimed the following:

Freshman, sophomore, junior, senior -> 4 year bachelor degree (some coming in from community colleges would run freshman/sophomore -> Associates degree, then transfer to a four year college to complete the bachelor)

Masters was commonly another two years, And doctorate is likely another

The CompSci sequence when I took it had the parallel tracks of Intro. FORTRAN, Adv. FORTRAN, Assembly Intro. COBOL, Adv. COBOL, Database (at the time -- a DBTG Network system; Relational was introduced as a "theoretical" development) (both tracks required)

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	Wulfraed                 Dennis Lee Bieber         AF6VN 
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Reply to
Dennis Lee Bieber

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