Is it a lost cause?

I know nothing of MACE, but a similar SWI was on the PDP11 which was especially a debug SWI.

However, a problem with that approach is if the restored instruction is a branck or a jump if you wish to single step. ISTR that the PDP11 (35 years ago for me!!!!) had a bit in the processor status that would force a further debug SWI after 1 instruction.

Reply to
gareth G4SDW GQRP #3339
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I hand assembled machine code for the Oric, a 3D Space Invaders game, and to resolve future debugging problems, not wishing to hand code the whole lot again, every few instructions put in 3 NOPs so that if necessary a jump could be patched in to jump to some correcting code before jumping back a bit later on.

Reply to
gareth G4SDW GQRP #3339

Try telling that to the legions of kids who used to publish their machine code in the now-defunct Popular Computing Weekly!

Reply to
gareth G4SDW GQRP #3339

Ou-of-order? Sounds like introduced bugs :-)

Reply to
gareth G4SDW GQRP #3339

Used in computing in 1974 when I was there for a year. They had a 'paper' version of it too.

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Reply to
Bob Eager

The T-bit.

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Bob Eager

One nice thing about the PDP8 documentation, a convention that we seem to have lost these days, is that you also got a complete description of all the I/O at the register level and how to drive it.

Reply to
gareth G4SDW GQRP #3339

True. Although it was very simple I/O. DMA and interrupts were fairly rarely used in practice.

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Reply to
Bob Eager

But once that you have such principles under your belt, then all I/O becomes simple for you; might take some winding of the handle and a little more time to program, but remains conceptually simple.

Reply to
gareth G4SDW GQRP #3339

It's nothing new, optimising compilers have been rearranging the order of execution for decades now, and pipeline processors have been reordering the submission of instructions to the execution hardware for a long time too - the PowerPC has an instruction with the wonderful mnemonic EIEIO, Enforce In order Execution of IO which can be used to prevent the CPU overlapping or reordering instructions in hardware drivers where the order matters for reasons the CPU cannot determine.

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Reply to
Ahem A Rivet's Shot

If you program PICS today, you might well do that in assembler, and there is no operating system there at all.

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Reply to
The Natural Philosopher

That sounds very like the ICL 1900 mainframes where I first learnt assembler (I'd previously learnt Algol 60 at uni). The 1900 only had two hardware registers, which held datum and limit addresses for the active program. Programs were a contiguous block of memory - task switching was done by changing datum and limit to point at the next program to run. Each program had its own register set because they were the first 8 words of each program, with word +8 being the PC and, since all addresses in a program were relative to datum, programs could be swapped in, out or moved in memory very simply.

Motorola 6809 and 68xxx chips partly shared these characteristics: although the registers etc were a single set implemented in hardware, it was possible to write a program using only PC-relative addressing, so again it could be swapped in or out and moved in RAM by the OS between its active time slices. Microware's OS-9 operating system (it ran on both

6809 and 68xxx chips) could and did do this because all programs written for it used PC-relative or indirect addressing.
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Martin Gregorie

A PLAN for man?

Reply to
gareth G4SDW GQRP #3339

How does 'sophomore' map onto a traditional British/NZ degree system, at least as I knew it? AQ BSc is/was usually three years with an MSc adding another year and the PhD taking a few years more after that.

I learnt Algol 60 before being exposed to assembler and found that useful since, by the time I learnt my first assembly language, I already understood the principles of conditional branches, loops and how to structure a program as a set of functions.

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Reply to
Martin Gregorie

second year undergraduate.

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Reply to
The Natural Philosopher

'now-defunct'

This the 21st century. Teach them what they need to know rather than what we did.

Reply to
Andrew Swallow

Not an unusual arrangement in those days. The PDP-10 had the same (with

16 x 36 bit registers).

In fact, in the more expensive systems (e.g. 1904) the registers (accumulatots, call them what you will) did appear as the first eight words of memory, but were in reality hardware based.

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Reply to
Bob Eager

In those days IIRC CPUS were built from logic chips, and RAM was not the same thing.

Only when single chip CPUS appeared wasit woirth puttng some RAM on te chip itself and calling it 'registers

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Reply to
The Natural Philosopher

Also in PDP11, the hardware registers were addressable as though they were memory locations on the I/O page.

Reply to
gareth G4SDW GQRP #3339

Teach them how to find out the things they need to know and inspire them to find out or invent more.

Reply to
gareth G4SDW GQRP #3339

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