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video processor VDP3116B line sync failure

[repeat post for a new thread, i.e. without mistaken references]

Hello!

A ten year old color TV set of mine with vacuum picture tube has recently lost its horizontal synchronization: the display shows the corresponding diagonal stripes, slanting from left to right. Vertical synchronization is functional however.

The entire video processing of the set is done by a Micronas VDP3116B processor in a 64-pin shrink-DIP package. I have checked those external voltages and signals that appear to be vital for its proper operation, and they all looked ok. The only symptom of misbehavior is that, with a video test signal with a synch-to-synch pulse distance of 63.9 us fed into the VDP default video input pin 63 (VIN3), the output signal on pin

50 (HOUT) shows the shorter period is 63.1 us, where a duty cycle of 50% moreover confirms the lack of synchronization, according to the VDP datasheet. The synch signal output on the unused pin 7 (FSY) has the wrong period of 63.1 us too, but here the duty cycle is around 7%, which looks ok.

The VDP3116B is configured by the control processor (an ST92R195) of the TV set via an I2C-bus interface; disconnecting the interface lines and using a hardware reset on the VDP3116B didn't restore horizontal synchronization (I believe the VDP default parameters should suffice for synch extraction). Nor did a replacement of the VDP3116B chip restore horizontal synchronization!

A wiring diagram of a closely related TV model is available at , almost everything of significance here is in agreement with my board). A 1998 version of the VDP3116B datasheet can be found at <

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Any suggestions? How can a working Micronas VDP3116B loose its ability to extract the horizontal synchronization of the input video signal?

Martin.

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clicliclic
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Might be an idea to check the flyback input on pin 13 could be used as a PLL reference.

John.

Reply to
John Ferrier

John Ferrier schrieb:

Thanks for looking into the matter!

I have checked the flyback signal that is fed to pin 13 (HFLB) of the VDP as this was one of the things that seemed critical. The signal is present and clean: HFLB levels are 0.15 V and 5.0 V, the duty cycle is around 14%, the rise and fall times (10% to 90%) are 45 ns and 25 ns, respectively.

Actually, the conditioning of the flyback signal from the capactive divíder C306/C307 is one of a few points in which my board differs from the schematic linked to above: the simple resistor (R771) plus two diodes (D701/D702) scheme must have been a bit dangerous (it was obviously copied from the application circuit in the VDP datasheet). On my board, this has been replaced by two capacitively coupled NPN transistor stages (i.e. the signal is inverted twice).

Another critical point that I checked is the digital supply voltage on pin 15 (VSUPD), as any drop of this below 4.5 V for more than 50 ns would kick the VDP into standby mode for 50 us, according to the datasheet. The variation of VSUPD (i.e. regular oscillatory spikes) remains within +- 100 mV of 4.91 V, however.

What now?

Martin.

Reply to
clicliclic

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