OT: Is this question too challenging for a BSEE graduate?

Then make your challenge on the proper newsgroup: news:sci.electronics.design which is where you'll find the EEs.

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Thank you Michael. I was not sure to which sci.electronics.* group I should post. Thanks for adding sci.electronics.design to this thread.

4 * 40 ohms = 160 !! 4 kohms

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It really is that simple, isn't it? My frustration that prompted my post is that recent BSEE graduates don't seem to be able to answer this question.

It's easier than either of the methods you propose; it's obvious by inspection. Just notice that the two resistors in the op-amp's positive input divider are in a 3:1 ratio, and so the same must be true for the ones in the negative divider. So the FET must be acting as a 120 ohm resistor.

Isaac

Sheesh! Graduate EEs can't get this? I'm "just a tech," but it took me about 13 seconds to get the answer, assuming I remember correctly that I=E/R:

((Vdc/4)/40) A.

Cheers! Rich

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r...

d d o

Graduates from where?

Nice carbine photos by the way.

(another) Michael

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It's not asking for I, but Req.

I agree with last poster as (160 * 4000) / (160 + 4000) ohms

But I would not get the answer under pressure, in an interview. I guess I am one of the bad EEs.

Since R2R1 is a voltage divider, the voltage on U1+ will be:

+VDC * R1 U1+ = ----------- R1 + R3

Now, since the voltage on U1- must be equal to the voltage on U1+, and since R(Q1)R3 is another voltage divider,

(+VDC * R3) - ((U1+) * R3) R(Q1) = ---------------------------- U1+

For the value, since the ratio of R2:R1 = 3 and the voltage across R1 and R3 are equal, the ratio of R(Q1) to R3 must also be 3, making the FET's resistance 3 * R3 = 120 ohms.

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JF

I'm posting this before looking at any of the other responses.

I'm always saying I'm smart because I look for the "fundamental principle" underlying things. So... Let's see if I am...

This is a clever trick question. It assumes you understand /the/ basic rule of op-amp circuit design -- if the circuit is stable, then the voltage difference between the inverting and non-inverting inputs must be zero (or in practice, vanishingly small).

Assuming Vdc is "stiff", then the voltage at the non-inverting input /must/ be Vdc/4. Right? The voltage at the inverting input /must/ be the same. Ergo, the resistance of the JFET must be three times R3, or 120 ohms. Right, too?

As the op amp draws no input current, the current through the JFET and R3 must be the same. Therefore, the load impedance must be 120 + 40.

QED?

Please note that only the most-trivial arithmetic is needed to solve the problem. No fancy-shmancy algebra.

Bob Pease would be proud. I hope.

R2 Rx ---- = ---- = 120 ohms R1 R3

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JF

*Real* EEs only use nodal analysis where there isn't an easier alternative. 30 seconds inspection gives R effective = 160, in parallel with 4k = 153.85 ohms.

There's another issue, though. Depending on choice of JFET (most, actually), the gate can go positive with respect to the source.

Nobody with any sense would use a JFET here. Rather a naïve example.

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"For a successful technology, reality must take precedence 
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It was the equivalent resistance of the *whole programmable load* that was asked for.

I did it this way:

The voltage at u1 + input is 1/(3+1)*VDC =VDC/4

Feedback will make the voltage across R3 also VDC/4, hence the current in Q1 and R3 will be VDC/(4*40*) = VDC/160

The resistance of that branch is therefore 160 ohms.

The whole load looks like 160ohms in parallel with 4000 ohms =

4000*160/(4000+160) = 153.85 ohms.

See my remarks in a previous post about Q1 gate going positive of its source.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

RosemontCrest wrote in news: snipped-for-privacy@26g2000yqv.googlegroups.com:

No, it's trivial.

Since the voltage at the inputs of the opamp is 0.25 * Vdc, the JFET drain/source current should be Vdc/160, or an equivalent resistance of 160 ohms. The divider is in parallel.

So..

Req = 160 || 4000 ~= 153.8 ohms.

Best regards, Spehro Pefhany

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To be honest I felt it wasn't obvious what the programmable load was. It's also unusual to call a ground referenced load - a load, although I agree it is, it does add to the confusion.

Also +VDC looks like a fixed voltage.

I would make it easier to interpret by saying:

VDC VDC | | circuit equiv to resistor | | GND GND

Apologies for non-fixed font if this gets messed up

To me question seems ambiguous. From a DC viewpoint, the JFET needs to conduct enough current to make the voltage across 40 ohms equal 1/4 of VDC so the JFET have to be 120 ohms. From an AC viewpoint, the JFET looks like zero ohms.

David

As I pointed out, this is a "trick" question intended to see whether the applicant understands "the basic principle of op-amp circuit design".

When I briefly attended CalTech, one of our physics tests had a question about the Doppler shift of a satellite transmitter passing directly overhead. You'd be amazed at how many students wasted time calculating it.

Spehro Pefhany wrote in news:Xns9E1A6190B2594speffinterlogcom@69.16.186.50:

One of the "issues" with this circuit lies in the interpretation of "ideal" for the op-amp. Here, I (and others) have ASS-U-MEd that it has infinite gain and zero offset voltage in zero input bias current, but also that it will swing negative using the single

+12/0 supply (for example, it might have a built-in charge-pump voltage converter). Most real op-amps won't do that, they'll swing down to somewhere near the lower rail. In which case, with a JFET, the op-amp will not be able to balance until the current exceeds Idss for the JFET. It also won't work much above Idss (regardless of the op-amp functionality) because the gate will begin to conduct, so it would have only a narrow range of operation over which it "looks" like a fixed resistor.

It will also behave differently if "+VDC" happens to be a negative voltage.

I don't think this is a very good "quiz" question, it leaves too many questions open and uses non-standard nomenclature. The proper answer to this one is probably "what are you trying to do?", the subtext being "whatever it is, this probably isn't going to do it".

Best regards, Spehro Pefhany

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"it's the network..."           "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info :  http://www.speff.com

I might be dead wrong, but it is a SUPERB question. It directly addresses the question... "Does the applicant UNDERSTAND what goes on in a stable op-amp circuit?"

The bottom line is that the "circuit" doesn't need the least bit of "analysis" at all. If you understand that, in a stable circuit, the inverting and non-inverting inputs have the same voltage on them, the solution is utterly trivial.