CLK3 , not from the USB chip, comes from VCO o/p of U3, a 74HCT4046 , whose sig in comes from U29 an 04 inverter whose input comes from pin33 of the CPLD functional blocks, which is firmly stuck logic H so vicious circle of inactivity. Incidently TP4 of 8 is the only one with any activity on , one of the approx
22MHz clocks. Will have to leave exploring this for a while and get back to bread and butter work, but any suggestions for hardware checking in the meantime, welcome