CMOS DRAM chips and static

Eeyore wrote in news: snipped-for-privacy@hotmail.com:

Why do you feel the need to insult someone that is trying to help you understand something?

A half amp is .5 coul/sec. This represents about 3.121 x10^18 electrons. A penny (1950 vintage) weighs about 3.1 gm and contains about 2.9 x 10^22 atoms. There are clearly quite a few electrons in that penny, but NOT a huge excess of electrons, normally.

Most chips have very small amounts of metal in them. Lets say the gate in question holds 1 mg of metal. (it is almost certainly MUCH less than that, but lets go with that for the moment) If it were copper, there would be about 9.3x10^18 atoms, so out of every three atoms, we would need to have 1 excess electron in order to have a charge of .5 coul.

The electric field is proportional to the charge and inversely proportional to the square of the distance between the charge centers(the dielectric thickness in this case)

A volt is a joule per coulomb.

For a parallel plate capacitor, V = q/C. so, what is the value of the capacitor we have charged inside that chip?

Lets say it is 1 pf. To charge the cap with .5 coul of electrons what voltage do we need? My calculations show 5x10^11 volts. That seems a bit over any gate rating I can imagine for any normal chips.

Even if the gate were 10 uF, a charge of half a coulomb would require 50 kV.

As I said before, current from charge on the chip is NOT a significant factor. VOLTAGE from charges on the chip ARE the hazard.

Do your own calculations and stop calling people names.

On Fri, 23 May 2008 01:05:05 +0100, Eeyore wrote:

...snip.....

charge

and

black

The safer practice nowadays is to use high resistance materials, and NOT aluminum foil, or metal film covered plastics, or that black conductive foam. The low resistance materials allow fast and high charge/discharge currents that can vapourize small tracks or microcircuitry. You should notice that a lot of packaging now uses those pink bags, and if you check with an ohmmeter, they appear to have an extremely high resistance. That allows voltages to dissipate with low (less damaging) current. The low resistance stuff is used to protect against external electric fields. If you have both situations, then put the component in a disipative bag (pink, high resistance), and then put that inside a conductive pouch, say aluminum foil. I'm told that you can effectively use the stuff that women commonly use to control static on their dress clothes. It's a spray can, I believe the active ingredient is sodium stearate (tallow?). It doesn't last forever, but for weeks or months it's not bad. There are commercial products that do a much better job, but you probably won't find them at your supermarket. It provides a dissipative ilm, and will not shield against electric fields. Some of the little plastic boxes are quite evil when it comes to voltage build up. You can flex one of those boxes, and easily build up a charge of 200v-2Kv on the inside surface. That charge can induce a a charge (and voltage) on a pin of a chip inside the box. I hade an old analog voltmeter with a pastic face, I rubbed the face, and the meter shifted about 10% because of the induced charge. One year later, it was still off by 5%. By opening it up and breathing on the inside plastic, I was able to eliminate the problem. I was really surprised at how long that charge was held! The statistics of ESD (Electro static discharge) suggest that the probability is quite high that no apparent damage will show up right away, but the component will be stressed, and will not live out its normal design lifetime. ESD problems are one of the biggest cause of poor reliability of microcircuitry. Check this site:

-Paul

PlPaul wrote in news: snipped-for-privacy@4ax.com:

Please show me where this is documented and what family of semi conductors to which it applies. My calculations show that the probability of producing excessive current flow inside a CMOS chip by use of aluminum foil, without already having exceeded the voltage limits of the chip, is very small.

It was well documented about 20-30 years ago. You're expected to KNOW this stuff now.

And what calculations are those ? Note : it has NOTHING to do with voltage.

Graham

It's the bloody DISCHARGE current through next to zero ohms that does the damage you fathead.

As well.

Stop talking ignorant DRIVEL and go learn something.

Ever wondered why tote bins for electronic parts are made of high resistivity black plastic and not aluminium ?

Just about EVERYONE in this thread has corrected your insane ideas yet you still presevere with them.

To create the anti-static effect, the black or silver bags are

***slightly***conductive

It's important to discharge at a slow rate,

The World's First Real ESD Safe Foam Amazing Constant Surface Resistivity 10^6 ? 10^7

Now go and take your IGNORANT ideas elsewhere.

Graham

Eeyore wrote in news: snipped-for-privacy@hotmail.com:

Says NOTHING about high current being a hazard.

This is for a floor mat, used to discharge the static build up of someone walking across a room. It has NO bearing upon your claim that a high CURRENT can be discharged from a chip causing damage to the chip WITHOUT the chip having a high static voltage on it to start with.

sales hype. No documentation claiming that high CURRENT is a hazard in the absence of a high voltage charge.

This MIGHT have some bearing on your claims in that the resistance specs for 'anti static foam' have a range of values, but it gives no other support for your claims.

Useless google search. Show me something that supports your claim, don't send me on a scavenger hunt.

I would rather learn than remain ignorant and spread apparently 'superstitious nonsense' as you appear to be doing.

I agree that for some things, such as shipping containers, conductive foam is better.

But I see absolutely no reason for not wrapping a sheet of aluminum foil around a chip to protect it [providing care is used in transferring the chip to the foil], or wrapping foil around some non conductive foam and then poking chips into the foam through the foil [again, taking care when picking up the chip and bringing it into contact with the foil].

I think your idea about high current discharge is WRONG, because, as I have tried to show you with a few calculations, there ain't enough electrons 'in the chip' to damage the chip due to high current UNLESS the chip has a high static charge on it already!

Since some chips can be damaged by voltages of 10 volts [ten!], the VOLTAGE is the hazard, NOT the current.

[quote from esdfunds1print.pdf from Many electronic components are susceptible to ESD damage at relatively low voltage levels. Many are susceptible at less than 100 volts and many disk drive components have sensitivities below 10 volts. [end quote]

There is quite a bit of interesting stuff on that web site but I see NOTHING about 'high current discharge' damage due to shorting pins of a chip together.

Again, I think that is pure nonsense. If you can support it, I will gladly change my opinion.

If you call me names and curse at me, I will stop reading your posts.

I am only willing to spend my time talking with those that have enough SELF RESPECT that they can afford to treat others with respect also.

First, there are a lot of differences between pink antistatic bags! they vary a lot in terms of what they are meant for, some are just for NON-ESD sensitive components, and many are meant as ESD dissipative bags.

Read this page

It discusses which kind of bags you should use for different applications. Notice that the low resistance ones are used for shielding (Faraday cage), and the pink ones (dissipative - hi R) are used to transport semiconductors.

Quotation from

: Resistance or resistivity measurements help define the material's ability to provide electrostatic shielding or charge dissipation. Electrostatic shielding attenuates electrostatic fields on the surface of a package in order to prevent a difference in electrical potential from existing inside the package. Electrostatic shielding is provided by materials that have a surface resistance equal to or less than 1.0 x 10^3 when tested according to EOS/ESD-S11.11 or a volume resistivity of equal to or less than 1.0 x 10^3 ohm-cm when tested according to the methods of EIA 541. In addition, shielding may be provided by packaging materials that provide an air gap between the package and the product. Dissipative materials provide charge dissipation characteristics. These materials have a surface resistance greater than 1.0 x 10^4 but less than or equal to 1.0 x 10^11 when tested according to EOS/ESD-S11.11 or a volume resistivity greater than 1.0 x

10^5 ohm-cm but less than or equal to 1.0 x 10^12 ohm-cm when tested according to the methods of EIA 541. ANSI/ESD 11.31 is used to evaluate the shielding characteristics of bags.

quotation from :

ESD-protective packaging materials must: 1) be dissipative; 2) exhibit low triboelectric charging tendency; and 3) have the ability to shield their contents from electrostatic fields. The insides of these packaging materials have a low charging layer, while their outer layers have a surface resistivity that's within the dissipative range. Dissipative materials have a surface resistance greater than 10^4 but less than or equal to 10^11 ohms when tested according to EOS/ESD-S11.11 or a volume resistivity greater than 1.0 x 10^5 ohm-cm but less than or equal to 1.0 x 10^12 ohm-cm when tested according to the methods of EIA 541.

quotation from:

Q. During the past few months I have been trying to change our old process of transporting our circuit boards around our factory from the use of 'CONDUCTIVE BAGS' to the use of 'DISSAPATIVE BAGS'. I have been unsuccessful due to the fact I cannot prove that this will benefit the reliability of our products. How can it be proven 'Practically' or 'Theoretically' to Justify the extra costs incurred in the use of dissipative bags? A. You have a good question. There is a white paper talking about discharge times that may help. The more conductive an item is, the greater the energy density in an ESD event. By slowing the charge transfer (ESD event) down with a more resistive material (dissipative), you can minimize the risks associated with conductive ESD events. With a dissipative material, instead of an ESD event, you will have a current ?bleeding? or charge balance that is better controlled.

read here:

this paper concerns itself most with events that are external to the bag

read here:

where the pink bags are at fault (because the ones used do not shield against external events)

a typical product that does BOTH jobs, dissipative and shielding:

papers: White Paper - ESD Phenomena and Reliability for Microelectronics, ESD Association, Oct., 2002

There are standards that discuss this and set requirements for conductive (the kind of containers you're talking about) and dissipative containers. Site:

standards: ANSI ESD S11.31-1994: Evaluating the Performance of Electrostatic Discharge Shielding Bags, ESD Association, Rome, NY 13440

ESD TR 20.20: ESD Handbook, ESD Association, Rome, NY 13440

although not quite relevant to the argument in this thread, you should read this guy's experiences and his discovered gotcha's about ESD products:

-Paul

Paul wrote in news: snipped-for-privacy@4ax.com:

VERY interesting. I am glad I started with reading this one. Will read the other references also and I thank you for them and the time you took to put them together.

It has been some time (over 30 years) since I worked on a production line and anti-static precautions were not taken. We made resistors and capacitors. It has been almost as long since I worked with radar and very ESD sensitive diodes. Since then, I have been lucky, I guess. In Baton Rouge, the high humidity helps. I have built some SMT devices recently, using ESD sensitive devices, working on a foil covered bench and making sure everything was at the foils potential. No problems but from the info in the above reference, I can see some places I could have run into problems if I did things differently.

Again, my thanks.

Piss off Terrell, you worthless loser.

Simply untrue.

Graham

A foil covered bench is a very bad idea.

Graham

Paul wrote in news: snipped-for-privacy@4ax.com:

The best bags to use are apparently the moisture resistant ones that have an anti static [moderate conductive layer to avoid attracting sparks], a highly conductive layer [Faraday shielding and good anti EMP shielding], another other anti static layer [again to avoid sparking] and are heat sealable and moisture proof. Pink bags are almost useless as are black bags as they do not protect the contents from high voltage impulses near the bag.

Nothing in ANY document I have seen so far says anything about a hazard due to shorting the leads of an IC TOGETHER.

There is mention of discharging an INDUCED charge, via a leg during some of the testing. The charge being induced in the assembly equipment by the motion of the chips through the storage and assembly equipment.

One of the surprising 'reminders' [I should have remembered it from physics] is that simply separating two conductors physically can induce a charge. In other words, picking up a chip that has been laying on a conductor or an insulator and lifting it vertically away from that surface can create an electrical potential between the two objects unless they both are grounded to a common point.

Thanks again for the interesting references.

I can actually remember aluminium tubes. They didn't stay around for long.

Graham

I can think of reasons for not having a foil-covered bench, but rapid discharge of static potentials isn't one of them.

I've wrapped ICs in aluminum foil when necessary, and never had any problem.

I'd agree that conductive foam is the best way to store ICs.

"William Sommerwerck" wrote in news:mPednTu94-URAqfVnZ2dnUVZ snipped-for-privacy@comcast.com:

Yeah. Like when working on an AC/DC 5 tube type radio chassis :)

I usually just cover a sheet of styrafoam with foil when I am putting together something that uses cmos chips like the

board. And no, that is NOT a picture of the one I built, mine is not that pretty, but it works!

Agreed.

On Mon, 26 May 2008 01:30:42 +0000 (UTC), bz wrote:

....snip!........

To get an idea of these voltages, you can make a crude electrometer by using a digital voltmeter that has 10M ohms input resistance, and a

1 volt sensitivity. Connect the "common" terminal to a ground (earthed). Connect a plate (say 3 in X 3 in.) through 10,000 Megohms to the 1 volt input. You now have a 1000-1 voltage divider, whose input is 10KM. If you scuff your feet on the floor, and touch the plate you should be able to read up to several hundred volts (taking the 1000-1 into account) as a result. You can get better results using a more sensitive voltage range, and using 100,000Megohms or 1 million megohms. The more sensitive of these devices can be used to pick up the voltage potentials on insulators. (small surfaces to be measured will require a smaller sense plate.) You have to be careful of the insulation resistance of any components or "insulators" with this device. These aren't your garden variety of resistors! I use the 1000-1 circuit to demonstrate to students the degree of voltages picked up during ordinary motions, and how well they are controlled by use of a grounding strap. To really show ESD, you need a charge measuring device that is calibrated, then it becomes real clear just how bad things can get.

There are some cases of chips being slid out of their antistatic tubes, the sliding action charged up the chips, (we assume the whole chip charged up). As the chips dropped onto a low resistance bench, they discharged through the pin that first touched the bench, and damaged the chip. Mechanical movement can induce a charged surface. One of the worst offenders is sticky tape.... Components are often delivered as "ammo-paks", or parts that are held in position by tape (like the belts of ammunition), so that they can be fed into a machine that removes them from the belt, and inserts the part into the circuit board or assembly. If you stick down a piece of masking tape onto some plastic, then tear it off, both the tape and the plastic will generate a high voltage. In a lot of cases, if it's dark, you can see sparks! That's a pretty nasty voltage! A lot of plastics and insulators generate significant voltage when they are flexed or rubbed. They can induce voltages in conductive surfaces nearby, because they set up a potential field around themselves. Just passing by one of these charged surfaces can induce voltages on components. that's why the much better static bags have both "dissipative" surfaces (on direct contact with the shipped chip) to allow gentle discharge currents, AND one or two layers of shielding surfaces to reduce the effect of induced voltages from nearby charged objects. For those reasons JPL prohibits the pink bags, and uses 3M #3370 bags, which have shielding, dissipative layers, low "outgassing", low contamination, and a good moisture resistance. The bags are just a small part of the overall program.... you need to have a very disciplined and comprehensive program in order to control ESD. That's where the ANSI/ESD S20.20-2007 comes into play, it ties together all the recommendations, standards, mil-specs, and practices into a standard that isn't scattered all over the place. This standard then refers to many other ANSI/ESD standards, each one specific to things like packaging, measuring, charge modelling, furniture, machinery, etc.

-Paul

Then you're either lucky or you had preciously observed good handling precautions, so foil wouldn't have given any trouble.

It absolutely is because it allows any stored charge to dissipate slowly without damage.

Graham

If you worked for any compnay I was involved with, you'd be handed your 'P45' PDQ.

Graham

P45 = leaving employment.

Which is why they should be deposited into an anti-static tote bin or onto an anti-static bench mat of 10^4 - 10^11 ohm/sq resistivity. Per EIA etc standards.

Graham

Paul wrote in news: snipped-for-privacy@4ax.com:

Nice idea on the 'electroscope'. Will play with the idea. I have a very high impedance tube type 'electrometer' from the 50's that was surplussed in the 70's. I remember looking at some of these effects back then.

That I believe. What I didn't believe was Eeyore's explanation that shorting the chips leads together caused damage due to the current flow caused by the stored charge flowing from one lead to the other.

Yes!

I have a chair that generates a charge when I stand up after sitting on it for a while.

I agree with what you are saying and appreciate the hazards of motion induced charges.

If I were working with very ESD sensitive chips on a daily basis, I would want a good work station, properly set up.

If I just need to put memory into a computer or build a device like the one I built recently, I will continue to use, with caution, the techniques I have used successfully in the past.

I will be a bit more cautious when moving things around, taking more time and steps to discharge 'induced charges'.

Thanks again.