Microchip PIC16 datasheet: 18.0 DC and AC characteristics graphs and tables

18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

"Typical" represents the mean of the distribution at 25°C. "Maximum" or "minimum" represents (mean + 3\sigma) or (mean – 3\sigma) respectively, where \sigma is a standard deviation, over the whole temperature range.

FIGURE 18-1: TYPICAL IDD vs. Fosc OVER VDD (HS MODE)

FIGURE 18-2: MAXIMUM IDD vs. Fosc OVER VDD (HS MODE)

FIGURE 18-3: TYPICAL IDD vs. Fosc OVER VDD (XT MODE)

FIGURE 18-4: MAXIMUM IDD vs. Fosc OVER VDD (XT MODE)

DS39582C-page 198 © 2001-2013 Microchip Technology Inc.

FIGURE 18-5: TYPICAL IDD vs. Fosc OVER VDD (LP MODE)

FIGURE 18-6: MAXIMUM IDD vs. Fosc OVER VDD (LP MODE)

FIGURE 18-7: AVERAGE Fosc vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25°C)

FIGURE 18-8: AVERAGE Fosc vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, +25°C)

DS39582C-page 200 © 2001-2013 Microchip Technology Inc.

FIGURE 18-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, +25°C)

FIGURE 18-10: IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED)

Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)

FIGURE 18-11: TYPICAL AND MAXIMUM \DeltaI${TMR1}$ vs. V${DD}$ OVER TEMPERATURE (-10°C TO +70°C, TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF)

FIGURE 18-12: TYPICAL AND MAXIMUM \DeltaI${WDT}$ vs. V${DD}$ OVER TEMPERATURE (WDT ENABLED)

DS39582C-page 202 © 2001-2013 Microchip Technology Inc.

FIGURE 18-13: \DeltaI${BOR}$ vs. V${DD}$ OVER TEMPERATURE

FIGURE 18-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. V$_{DD}$ (-40°C TO +125°C)

FIGURE 18-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C)

FIGURE 18-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C)

DS39582C-page 204 © 2001-2013 Microchip Technology Inc.

FIGURE 18-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C)

FIGURE 18-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C)

FIGURE 18-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C)

FIGURE 18-20: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C)

DS39582C-page 206 © 2001-2013 Microchip Technology Inc.

FIGURE 18-21: MINIMUM AND MAXIMUM V${IN}$ VS. V${DD}$ (ST INPUT, -40°C TO +125°C)

FIGURE 18-22: MINIMUM AND MAXIMUM V${IN}$ VS. V${DD}$ (I$^2$C INPUT, -40°C TO +125°C)

FIGURE 18-23: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C)

FIGURE 18-24: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C)

DS39582C-page 208 © 2001-2013 Microchip Technology Inc.

19.0 PACKAGING INFORMATION

19.1 Package Marking Information

40-Lead PDIP

Example

44-Lead TQFP

Example

44-Lead PLCC

Example

Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week '01') NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn)

• This package is Pb-free. The Pb-free JEDEC designator (e3) can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

Package Marking Information (Cont’d)

44-Lead QFN

Example

DS39582C-page 210 © 2001-2013 Microchip Technology Inc.

40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

• Controlling Parameter
  § Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016

44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

• Controlling Parameter
  § Significant Characteristic

Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076

44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

• Controlling Parameter
  § Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048

44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

*Controlling Parameter

Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: M0-220 Drawing No. C04-103

28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

• Controlling Parameter
  § Significant Characteristic

Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070

28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

• Controlling Parameter
  § Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052

28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

• Controlling Parameter
  § Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073

28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

*Controlling Parameter

Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: mMO-220

Drawing No. C04-114

APPENDIX A: REVISION HISTORY

Revision A (November 2001)

Original data sheet for PIC16F87XA devices. The devices presented are enhanced versions of the PIC16F87X microcontrollers discussed in the “PIC16F87X Data Sheet” (DS30292).

Revision B (October 2003)

This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section 17.0 “Electrical Characteristics” have been updated and there have been minor corrections to the data sheet text.

Revision C (January 2013)

Added a note to each package outline drawing.

APPENDIX B: DEVICE DIFFERENCES

The differences between the devices in this data sheet are listed in Table B-1.

TABLE B-1: DIFFERENCES BETWEEN DEVICES IN THE PIC16F87XA FAMILY

APPENDIX C: CONVERSION CONSIDERATIONS

Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.

TABLE C-1: CONVERSION CONSIDERATIONS

INDEX

A

• A/D ........ 127
• Acquisition Requirements ........ 130
• ADCON0 Register ........ 127
• ADCON1 Register ........ 127
• ADIF Bit ........ 129
• ADRESH Register ........ 127
• ADRESL Register ........ 127
• Analog Port Pins ........ 49, 51
• Associated Registers and Bits ........ 133
• Calculating Acquisition Time ........ 130
• Configuring Analog Port Pins ........ 131
• Configuring the Interrupt ........ 129
• Configuring the Module ........ 129
• Conversion Clock ........ 131
• Conversions ........ 132
• Converter Characteristics ........ 194
• Effects of a Reset ........ 133
• GO/DONE Bit ........ 129
• Internal Sampling Switch (Rss) Impedance ........ 130
• Operation During Sleep ........ 133
• Result Registers ........ 132
• Source Impedance ........ 130
• A/D Conversion Requirements ........ 195
• Absolute Maximum Ratings ........ 173
• ACKSTAT ........ 101
• ADCON0 Register ........ 19
• ADCON1 Register ........ 20 Addressable Universal Synchronous Asynchronous
   Receiver Transmitter. See USART.
• ADRESH Register ........ 19
• ADRESL Register ........ 20 Analog-to-Digital Converter. See A/D.
  Application Notes
   AN552 (Implementing Wake-up
• on Key Stroke) ........ 44
• AN556 (Implementing a Table Read) ........ 30 Assembler
• MPASM Assembler ........ 167 Asynchronous Reception
• Associated Registers ........ 118, 120 Asynchronous Transmission
• Associated Registers ........ 116

B

• Banking, Data Memory ........ 16, 22

• Baud Rate Generator ........ 97

• Associated Registers ........ 113

• BCLIF ........ 28

• BF ........ 101 Block Diagrams

• A/D ........ 129

• Analog Input Model ........ 130, 139

• Baud Rate Generator ........ 97

• Capture Mode Operation ........ 65

• Comparator I/O Operating Modes ........ 136

• Comparator Output ........ 138

• Comparator Voltage Reference ........ 142

• Compare Mode Operation ........ 66  Crystal/Ceramic Resonator Operation

• (HS, XT or LP Osc Configuration) ........ 145  External Clock Input Operation

• (HS, XT or LP Osc Configuration) ........ 145

• Interrupt Logic ........ 153

• MSSP (I²C Mode) ........ 80

• MSSP (SPI Mode) ........ 71

• On-Chip Reset Circuit ........ 147

• PIC16F873A/PIC16F876A Architecture ........ 6

• PIC16F874A/PIC16F877A Architecture ........ 7 PORTC
   Peripheral Output Override

• (RC2:0, RC7:5) Pins ........ 46

• Peripheral Output Override (RC4:3) Pins ........ 46

• PORTD (in I/O Port Mode) ........ 48

• PORTD and PORTE (Parallel Slave Port) ........ 51

• PORTE (In I/O Port Mode) ........ 49

• RA3:RA0 Pins ........ 41

• RA4/T0CKI Pin ........ 42

• RA5 Pin ........ 42

• RB3:RB0 Pins ........ 44

• RB7:RB4 Pins ........ 44

• RC Oscillator Mode ........ 146

• Recommended MCLR Circuit ........ 148

• Simplified PWM Mode ........ 67

• Timer0/WDT Prescaler ........ 53

• Timer1 ........ 58

• Timer2 ........ 61

• USART Receive ........ 117, 119

• USART Transmit ........ 115

• Watchdog Timer ........ 155 BOR. See Brown-out Reset.
  BRG. See Baud Rate Generator.

• BRGH Bit ........ 113

• Brown-out Reset (BOR) ........ 143, 147, 148, 149, 150

• BOR Status (BOR Bit) ........ 29

• Bus Collision During a Repeated Start Condition ........ 108

• Bus Collision During a Start Condition ........ 106

• Bus Collision During a Stop Condition ........ 109

• Bus Collision Interrupt Flag bit, BCLIF ........ 28

C

C Compilers

• MPLAB C17 ........ 168
• MPLAB C18 ........ 168
• MPLAB C30 ........ 168
• Capture/Compare/PWM (CCP) ........ 63  Associated Registers
• Capture, Compare and Timer1 ........ 68
• PWM and Timer2 ........ 69
• Capture Mode ........ 65
• CCP1IF ........ 65
• Prescaler ........ 65
• CCP Timer Resources ........ 63  Compare
• Special Event Trigger Output of CCP1 ........ 66
• Special Event Trigger Output of CCP2 ........ 66
• Compare Mode ........ 66
• Software Interrupt Mode ........ 66
• Special Event Trigger ........ 66
• Interaction of Two CCP Modules (table) ........ 63
• PWM Mode ........ 67
• Duty Cycle ........ 67
• Example Frequencies/Resolutions (table) ........ 68
• PWM Period ........ 67
• Special Event Trigger and A/D Conversions ........ 66

Capture/Compare/PWM Requirements

• (CCPI and CCP2) ........ 186 CCP. See Capture/Compare/PWM.
• CCP1CON Register ........ 19
• CCP2CON Register ........ 19
• CCPR1H Register ........ 19, 63
• CCPR1L Register ........ 19, 63
• CCPR2H Register ........ 19, 63
• CCPR2L Register ........ 19, 63
• CCPxM0 Bit ........ 64
• CCPxM1 Bit ........ 64
• CCPxM2 Bit ........ 64
• CCPxM3 Bit ........ 64
• CCPxX Bit ........ 64
• CCPxY Bit ........ 64
• CLKO and I/O Timing Requirements ........ 183
• CMCON Register ........ 20 Code Examples
• Call of a Subroutine in Page 1 from Page 0 ........ 30
• Indirect Addressing ........ 31
• Initializing PORTA ........ 41
• Loading the SSPBUF (SSPSR) Register ........ 74
• Reading Data EEPROM ........ 35
• Reading Flash Program Memory ........ 36 Saving Status, W and PCLATH Registers
• in RAM ........ 154
• Writing to Data EEPROM ........ 35
• Writing to Flash Program Memory ........ 38
• Code Protection ........ 143, 157
• Comparator Module ........ 135 Analog Input Connection
• Considerations ........ 139
• Associated Registers ........ 140
• Configuration ........ 136
• Effects of a Reset ........ 139
• Interrupts ........ 138
• Operation ........ 137
• Operation During Sleep ........ 139
• Outputs ........ 137
• Reference ........ 137
• Response Time ........ 137
• Comparator Specifications ........ 180
• Comparator Voltage Reference ........ 141
• Associated Registers ........ 142
• Computed GOTO ........ 30
• Configuration Bits ........ 143
• Configuration Word ........ 144
• Conversion Considerations ........ 220
• CVRCON Register ........ 20

D

Data EEPROM and Flash Program Memory

• EEADR Register ........ 33
• EEADRH Register ........ 33
• EECON1 Register ........ 33
• EECON2 Register ........ 33
• EEDATA Register ........ 33
• EEDATH Register ........ 33

Data EEPROM Memory

• Associated Registers ........ 39
• EEADR Register ........ 33
• EEADRH Register ........ 33
• EECON1 Register ........ 33
• EECON2 Register ........ 33
• Operation During Code-Protect ........ 39
• Protection Against Spurious Writes ........ 39
• Reading ........ 35
• Write Complete Flag Bit (EEIF) ........ 33
• Writing ........ 35
• Data Memory ........ 16
• Bank Select (RP1:RP0 Bits) ........ 16, 22
• General Purpose Registers ........ 16
• Register File Map ........ 17, 18
• Special Function Registers ........ 19
• DC and AC Characteristics Graphs and Tables ........ 197
• DC Characteristics ........ 175–179 Demonstration Boards
• PICDEM 1 ........ 170
• PICDEM 17 ........ 170
• PICDEM 18R PIC18C601/801 ........ 171
• PICDEM 2 Plus ........ 170
• PICDEM 3 PIC16C92X ........ 170
• PICDEM 4 ........ 170
• PICDEM LIN PIC16C43X ........ 171
• PICDEM USB PIC16C7X5 ........ 171
• PICDEM.net Internet/Ethernet ........ 170
• Development Support ........ 167
• Device Differences ........ 219
• Device Overview ........ 5
• Direct Addressing ........ 31

E

• EEADR Register ........ 21, 33
• EEADRH Register ........ 21, 33
• EECON1 Register ........ 21, 33
• EECON2 Register ........ 21, 33
• EEDATA Register ........ 21
• EEDATH Register ........ 21
• Electrical Characteristics ........ 173
• Errata ........ 4
• Evaluation and Programming Tools ........ 171
• External Clock Timing Requirements ........ 182 External Interrupt Input (RB0/INT). See Interrupt Sources.
• External Reference Signal ........ 137

F

• Firmware Instructions ........ 159 Flash Program Memory
• Associated Registers ........ 39
• EECON1 Register ........ 33
• EECON2 Register ........ 33
• Reading ........ 36
• Writing ........ 37
• FSR Register ........ 19, 20, 31

G

• General Call Address Support ........ 94

I

• I/O Ports ........ 41
• I2C Bus Data Requirements ........ 192
• I²C Bus Start/Stop Bits Requirements ........ 191 I²C Mode
• Registers ........ 80
• I²C Mode ........ 80
• ACK Pulse ........ 84, 85
• Acknowledge Sequence Timing ........ 104
• Baud Rate Generator ........ 97 Bus Collision
• Repeated Start Condition ........ 108
• Start Condition ........ 106
• Stop Condition ........ 109
• Clock Arbitration ........ 98
• Effect of a Reset ........ 105
• General Call Address Support ........ 94
• Master Mode ........ 95
• Operation ........ 96
• Repeated Start Timing ........ 100
• Master Mode Reception ........ 101
• Master Mode Start Condition ........ 99
• Master Mode Transmission ........ 101 Multi-Master Communication, Bus Collision
• and Arbitration ........ 105
• Multi-Master Mode ........ 105
• Read/Write Bit Information (R/W Bit) ........ 84, 85
• Serial Clock (RC3/SCK/SCL) ........ 85
• Slave Mode ........ 84
• Addressing ........ 84
• Reception ........ 85
• Transmission ........ 85
• Sleep Operation ........ 105
• Stop Condition Timing ........ 104
• ID Locations ........ 143, 157
• In-Circuit Debugger ........ 143, 157
• Resources ........ 157
• In-Circuit Serial Programming (ICSP) ........ 143, 158
• INDF Register ........ 19, 20, 31
• Indirect Addressing ........ 31
• FSR Register ........ 16
• Instruction Format ........ 159
• Instruction Set ........ 159
• ADDLW ........ 161
• ADDWF ........ 161
• ANDLW ........ 161
• ANDWF ........ 161
• BCF ........ 161
• BSF ........ 161
• BTFSC ........ 161
• BTFSS ........ 161
• CALL ........ 162
• CLRF ........ 162
• CLRW ........ 162
• CLRWDT ........ 162
• COMF ........ 162
• DECF ........ 162
• DECFSZ ........ 163
• GOTO ........ 163
• INCF ........ 163
• INCFSZ ........ 163
• IORLW ........ 163
• IORWF ........ 163
• RETURN ........ 164
• RLF ........ 164
• RRF ........ 164
• SLEEP ........ 164
• SUBLW ........ 164
• SUBWF ........ 164
• SWAPF ........ 165
• XORLW ........ 165
• XORWF ........ 165
• Summary Table ........ 160 INT Interrupt (RBO/INT). See Interrupt Sources.
• INTCON Register ........ 24
• GIE Bit ........ 24
• INTE Bit ........ 24
• INTF Bit ........ 24
• PEIE Bit ........ 24
• RBIE Bit ........ 24
• RBIF Bit ........ 24, 44
• TMR0IE Bit ........ 24
• TMR0IF Bit ........ 24 Inter-Integrated Circuit. See I²C.
• Internal Reference Signal ........ 137
• Internal Sampling Switch (Rss) Impedance ........ 130
• Interrupt Sources ........ 143, 153
• Interrupt-on-Change (RB7:RB4) ........ 44
• RBO/INT Pin, External ........ 9, 11, 154
• TMR0 Overflow ........ 154
• USART Receive/Transmit Complete ........ 111 Interrupts
• Bus Collision Interrupt ........ 28
• Synchronous Serial Port Interrupt ........ 26
• Interrupts, Context Saving During ........ 154 Interrupts, Enable Bits
• Global Interrupt Enable (GIE Bit) ........ 24, 153 Interrupt-on-Change (RB7:RB4)
• Enable (RBIE Bit) ........ 24, 154
• Peripheral Interrupt Enable (PEIE Bit) ........ 24
• RBO/INT Enable (INTE Bit) ........ 24
• TMR0 Overflow Enable (TMR0IE Bit) ........ 24 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag
• (RBIF Bit) ........ 24, 44, 154
• RBO/INT Flag (INTF Bit) ........ 24
• TMR0 Overflow Flag (TMR0IF Bit) ........ 24, 154

L

• Loading of PC ........ 30
• Low-Voltage ICSP Programming ........ 158
• Low-Voltage In-Circuit Serial Programming ........ 143

M

• Master Clear (\overlineMCLR) ........ 8
• MCLR Reset, Normal Operation ........ 147, 149, 150
• MCLR Reset, Sleep ........ 147, 149, 150 Master Synchronous Serial Port (MSSP). See MSSP.
• MCLR ........ 148
• MCLR/VPP ........ 10
• Memory Organization ........ 15
• Data EEPROM Memory ........ 33
• Data Memory ........ 16
• Flash Program Memory ........ 33
• Program Memory ........ 15 MPLAB ASM30 Assembler, Linker, Librarian ... 168
• MPLAB ICD 2 In-Circuit Debugger ........ 169 MPLAB ICE 2000 High-Performance Universal
• In-Circuit Emulator ........ 169

MPLAB ICE 4000 High-Performance Universal

• In-Circuit Emulator ........ 169 MPLAB Integrated Development
• Environment Software ........ 167
• MPLINK Object Linker/MPLIB Object Librarian ........ 168
• MSSP ........ 71 I²C Mode. See I²C.
• SPI Mode ........ 71 SPI Mode. See SPI. MSSP Module
• Clock Stretching ........ 90
• Clock Synchronization and the CKP Bit ........ 91
• Control Registers (General) ........ 71
• Operation ........ 84
• Overview ........ 71
• SPI Master Mode ........ 76
• SPI Slave Mode ........ 77
• SSPBUF ........ 76
• SSPSR ........ 76
• Multi-Master Mode ........ 105

O

• Opcode Field Descriptions ........ 159
• OPTION_REG Register ........ 23
• INTEDG Bit ........ 23
• PS2:PS0 Bits ........ 23
• PSA Bit ........ 23
• RBPU Bit ........ 23
• T0CS Bit ........ 23
• T0SE Bit ........ 23
• OSC1/CLKI Pin ........ 8, 10
• OSC2/CLKO Pin ........ 8, 10 Oscillator Configuration
• HS ........ 145, 149
• LP ........ 145, 149
• RC ........ 145, 146, 149
• XT ........ 145, 149
• Oscillator Selection ........ 143
• Oscillator Start-up Timer (OST) ........ 143, 148
• Oscillator, WDT ........ 155 Oscillators
• Capacitor Selection ........ 146
• Ceramic Resonator Selection ........ 145
• Crystal and Ceramic Resonators ........ 145
• RC ........ 146

P

Package Information

• Marking ........ 209

• Packaging Information ........ 209

• Paging, Program Memory ........ 30

• Parallel Slave Port (PSP) ........ 13, 48, 51

• Associated Registers ........ 52

• RE0/RD/AN5 Pin ........ 49, 51

• RE1/WR/AN6 Pin ........ 49, 51

• RE2/CS/AN7 Pin ........ 49, 51

• Select (PSPMODE Bit) ........ 48, 49, 50, 51 Parallel Slave Port Requirements

• (PIC16F874A/ 877A Only) ........ 187

• PCL Register ........ 19, 20, 30

• PCLATH Register ........ 19, 20, 30

• PCON Register ........ 20, 29, 149

• BOR Bit ........ 29

• POR Bit ........ 29

• PIC16F87XA Product Identification System ........ 231

• PICkit 1 Flash Starter Kit ........ 171

• PICSTART Plus Development Programmer ........ 169

• PIE1 Register ........ 20, 25

• PIE2 Register ........ 20, 27 Pinout Descriptions

• PIC16F873A/PIC16F876A ........ 8

• PIR1 Register ........ 19, 26

• PIR2 Register ........ 19, 28

• POP ........ 30 POR. See Power-on Reset.

• PORTA ........ 8, 10

• Associated Registers ........ 43

• Functions ........ 43

• PORTA Register ........ 19, 41

• TRISA Register ........ 41

• PORTB ........ 9, 11

• Associated Registers ........ 45

• Functions ........ 45

• PORTB Register ........ 19, 44

• Pull-up Enable (RBPU Bit) ........ 23

• RB0/INT Edge Select (INTEDG Bit) ........ 23

• RB0/INT Pin, External ........ 9, 11, 154

• RB7:RB4 Interrupt-on-Change ........ 154 RB7:RB4 Interrupt-on-Change Enable

• (RBIE Bit) ........ 24, 154 RB7:RB4 Interrupt-on-Change Flag

• (RBIF Bit) ........ 24, 44, 154

• TRISB Register ........ 21, 44

• PORTB Register ........ 21

• PORTC ........ 9, 12

• Associated Registers ........ 47

• Functions ........ 47

• PORTC Register ........ 19, 46

• RC3/SCK/SCL Pin ........ 85

• RC6/TX/CK Pin ........ 112

• RC7/RX/DT Pin ........ 112, 113

• TRISC Register ........ 46, 111

• PORTD ........ 13, 51

• Associated Registers ........ 48

• Functions ........ 48

• Parallel Slave Port (PSP) Function ........ 48

• PORTD Register ........ 19, 48

• TRISD Register ........ 48

• PORTE ........ 13

• Analog Port Pins ........ 49, 51

• Associated Registers ........ 50

• Functions ........ 49

• Input Buffer Full Status (IBF Bit) ........ 50

• Input Buffer Overflow (IBOV Bit) ........ 50

• Output Buffer Full Status (OBF Bit) ........ 50

• PORTE Register ........ 19, 49

• PSP Mode Select (PSPMODE Bit) ........ 48, 49, 50, 51

• RE0/RD/AN5 Pin ........ 49, 51

• RE1/WR/AN6 Pin ........ 49, 51

• RE2/CS/AN7 Pin ........ 49, 51

• TRISE Register ........ 49 Postscaler, WDT

• Assignment (PSA Bit) ........ 23

• Rate Select (PS2:PS0 Bits) ........ 23 Power-down Mode. See Sleep.

• Power-on Reset (POR) ........ 143, 147, 148, 149, 150

• POR Status (POR Bit) ........ 29

• Power Control (PCON) Register ........ 149

• Power-down (PD Bit) ........ 22, 147

• Power-up Timer (PWRT) ........ 143

• Time-out (TO Bit) ........ 22, 147

DS39582C-page 224 © 2001-2013 Microchip Technology Inc.

• Power-up Timer (PWRT) ........ 148
• PR2 Register ........ 20, 61 Prescaler, Timer0
• Assignment (PSA Bit) ........ 23
• Rate Select (PS2:PS0 Bits) ........ 23
• PRO MATE II Universal Device Programmer ........ 169 Program Counter
• Reset Conditions ........ 149
• Program Memory ........ 15
• Interrupt Vector ........ 15
• Paging ........ 30  Program Memory Map and Stack
• (PIC16F873A/874A) ........ 15  Program Memory Map and Stack
• (PIC16F876A/877A) ........ 15
• Reset Vector ........ 15
• Program Verification ........ 157
• Programming Pin (VPP) ........ 8
• Programming, Device Instructions ........ 159 PSP. See Parallel Slave Port.
  Pulse Width Modulation. See Capture/Compare/PWM,
   PWM Mode.
• PUSH ........ 30

R

• RA0/AN0 Pin ........ 8, 10

• RA1/AN1 Pin ........ 8, 10

• RA2/AN2/VREF-/CVREF Pin ........ 8, 10

• RA3/AN3/VREF+ Pin ........ 8, 10

• RA4/T0CKI/C1OUT Pin ........ 8, 10

• RA5/AN4/SS/C2OUT Pin ........ 8, 10 RAM. See Data Memory.

• RB0/INT Pin ........ 9, 11

• RB1 Pin ........ 9, 11

• RB2 Pin ........ 9, 11

• RB3/PGM Pin ........ 9, 11

• RB4 Pin ........ 9, 11

• RB5 Pin ........ 9, 11

• RB6/PGC Pin ........ 9, 11

• RB7/PGD Pin ........ 9, 11

• RC0/T1OSO/T1CKI Pin ........ 9, 12

• RC1/T1OSI/CCP2 Pin ........ 9, 12

• RC2/CCP1 Pin ........ 9, 12

• RC3/SCK/SCL Pin ........ 9, 12

• RC4/SDI/SDA Pin ........ 9, 12

• RC5/SDO Pin ........ 9, 12

• RC6/TX/CK Pin ........ 9, 12

• RC7/RX/DT Pin ........ 9, 12

• RCREG Register ........ 19

• RCSTA Register ........ 19

• ADDEN Bit ........ 112

• CREN Bit ........ 112

• FERR Bit ........ 112

• OERR Bit ........ 112

• RX9 Bit ........ 112

• RX9D Bit ........ 112

• SPEN Bit ........ 111, 112

• SREN Bit ........ 112

• RD0/PSP0 Pin ........ 13

• RD1/PSP1 Pin ........ 13

• RD2/PSP2 Pin ........ 13

• RD3/PSP3 Pin ........ 13

• RD4/PSP4 Pin ........ 13

• RD5/PSP5 Pin ........ 13

• RD6/PSP6 Pin ........ 13

• RD7/PSP7 Pin ........ 13

• RE0/RD/AN5 Pin ........ 13

• RE1/WR/AN6 Pin ........ 13

• RE2/CS/AN7 Pin ........ 13

• Read-Modify-Write Operations ........ 159

• Register File ........ 16

• Register File Map (PIC16F873A/874A) ........ 18

• Register File Map (PIC16F876A/877A) ........ 17 Registers

• ADCON0 (A/D Control 0) ........ 127

• ADCON1 (A/D Control 1) ........ 128  CCP1CON/CCP2CON (CCP Control 1

• and CCP Control 2) ........ 64

• CMCON (Comparator Control) ........ 135  CVRCON (Comparator Voltage

• Reference Control) ........ 141

• EECON1 (EEPROM Control 1) ........ 34

• FSR ........ 31

• INTCON ........ 24

• OPTION_REG ........ 23, 54

• PCON (Power Control) ........ 29

• PIE1 (Peripheral Interrupt Enable 1) ........ 25

• PIE2 (Peripheral Interrupt Enable 2) ........ 27

• PIR1 (Peripheral Interrupt Request 1) ........ 26

• PIR2 (Peripheral Interrupt Request 2) ........ 28

• RCSTA (Receive Status and Control) ........ 112

• Special Function, Summary ........ 19

• SSPCON (MSSP Control 1, I²C Mode) ........ 82

• SSPCON (MSSP Control 1, SPI Mode) ........ 73

• SSPCON2 (MSSP Control 2, I²C Mode) ........ 83

• SSPSTAT (MSSP Status, I²C Mode) ........ 81

• SSPSTAT (MSSP Status, SPI Mode) ........ 72

• Status ........ 22

• T1CON (Timer1 Control) ........ 57

• T2CON (Timer2 Control) ........ 61

• TRISE Register ........ 50

• TXSTA (Transmit Status and Control) ........ 111

• Reset ........ 143, 147  Brown-out Reset (BOR). See Brown-out Reset (BOR).
   MCLR Reset. See MCLR.
   Power-on Reset (POR). See Power-on Reset (POR).

• Reset Conditions for PCON Register ........ 149

• Reset Conditions for Program Counter ........ 149

• Reset Conditions for Status Register ........ 149  WDT Reset. See Watchdog Timer (WDT).
  Reset, Watchdog Timer, Oscillator Start-up Timer,
   Power-up Timer and Brown-out Reset

• Requirements ........ 184

• Revision History ........ 219

S

SCI. See USART.

• SCK ........ 71
• SDI ........ 71
• SDO ........ 71
• Serial Clock, SCK ........ 71 Serial Communication Interface. See USART.
• Serial Data In, SDI ........ 71
• Serial Data Out, SDO ........ 71 Serial Peripheral Interface. See SPI.
• Slave Select Synchronization ........ 77
• Slave Select, SS ........ 71
• Sleep ........ 143, 147, 156
• Software Simulator (MPLAB SIM) ........ 168
• Software Simulator (MPLAB SIM30) ........ 168
• SPBRG Register ........ 20
• Special Features of the CPU ........ 143

• Special Function Registers ........ 19
• Special Function Registers (SFRs) ........ 19
• Speed, Operating ........ 1
• SPI Mode ........ 71, 77
• Associated Registers ........ 79
• Bus Mode Compatibility ........ 79
• Effects of a Reset ........ 79
• Enabling SPI I/O ........ 75
• Master Mode ........ 76
• Master/Slave Connection ........ 75
• Serial Clock ........ 71
• Serial Data In ........ 71
• Serial Data Out ........ 71
• Slave Select ........ 71
• Slave Select Synchronization ........ 77
• Sleep Operation ........ 79
• SPI Clock ........ 76
• Typical Connection ........ 75
• SPI Mode Requirements ........ 190
• SS ........ 71 SSP
• SPI Master/Slave Connection ........ 75
• SSPADD Register ........ 20
• SSPBUF Register ........ 19
• SSPCON Register ........ 19
• SSPCON2 Register ........ 20
• SSPIF ........ 26
• SSPOV ........ 101
• SSPSTAT Register ........ 20
• R/W Bit ........ 84, 85
• Stack ........ 30
• Overflows ........ 30
• Underflow ........ 30 Status Register
• C Bit ........ 22
• DC Bit ........ 22
• IRP Bit ........ 22
• PD Bit ........ 22, 147
• RP1:RP0 Bits ........ 22
• TO Bit ........ 22, 147
• Z Bit ........ 22 Synchronous Master Reception
• Associated Registers ........ 123 Synchronous Master Transmission
• Associated Registers ........ 122
• Synchronous Serial Port Interrupt ........ 26 Synchronous Slave Reception
• Associated Registers ........ 125 Synchronous Slave Transmission
• Associated Registers ........ 125

T

• T1CKPS0 Bit ........ 57

• T1CKPS1 Bit ........ 57

• T1CON Register ........ 19

• T1OSCEN Bit ........ 57

• T1SYNC Bit ........ 57

• T2CKPS0 Bit ........ 61

• T2CKPS1 Bit ........ 61

• T2CON Register ........ 19

• TAD ........ 131

• Time-out Sequence ........ 148

• Timer0 ........ 53

• Associated Registers ........ 55

• Clock Source Edge Select (T0SE Bit) ........ 23

• Clock Source Select (T0CS Bit) ........ 23

• External Clock ........ 54

• Interrupt ........ 53

• Overflow Enable (TMR0IE Bit) ........ 24

• Overflow Flag (TMR0IF Bit) ........ 24, 154

• Overflow Interrupt ........ 154

• Prescaler ........ 54

• T0CKI ........ 54

• Timer0 and Timer1 External Clock Requirements ........ 185

• Timer1 ........ 57

• Associated Registers ........ 60

• Asynchronous Counter Mode ........ 59

• Reading and Writing to ........ 59

• Counter Operation ........ 58

• Operation in Timer Mode ........ 58

• Oscillator ........ 59

• Capacitor Selection ........ 59

• Prescaler ........ 60

• Resetting of Timer1 Registers ........ 60

• Resetting Timer1 Using a CCP Trigger Output ........ 59

• Synchronized Counter Mode ........ 58

• TMR1H ........ 59

• TMR1L ........ 59

• Timer2 ........ 61

• Associated Registers ........ 62

• Output ........ 62

• Postscaler ........ 61

• Prescaler ........ 61

• Prescaler and Postscaler ........ 62 Timing Diagrams

• A/D Conversion ........ 195

• Acknowledge Sequence ........ 104

• Asynchronous Master Transmission ........ 116  Asynchronous Master Transmission

• (Back to Back) ........ 116

• Asynchronous Reception ........ 118  Asynchronous Reception with

• Address Byte First ........ 120  Asynchronous Reception with

• Address Detect ........ 120

• Baud Rate Generator with Clock Arbitration ........ 98  BRG Reset Due to SDA Arbitration During

• Start Condition ........ 107

• Brown-out Reset ........ 184  Bus Collision During a Repeated

• Start Condition (Case 1) ........ 108  Bus Collision During Repeated

• Start Condition (Case 2) ........ 108  Bus Collision During Start Condition

• (SCL = 0) ........ 107  Bus Collision During Start Condition

• (SDA Only) ........ 106  Bus Collision During Stop Condition

• (Case 1) ........ 109  Bus Collision During Stop Condition

• (Case 2) ........ 109

• Bus Collision for Transmit and Acknowledge ........ 105

• Capture/Compare/PWM (CCP1 and CCP2) ........ 186

• CLKO and I/O ........ 183

• Clock Synchronization ........ 91

• External Clock ........ 182

• First Start Bit ........ 99

• I²C Bus Data ........ 191

• I²C Bus Start/Stop Bits ........ 190

• I²C Master Mode (Reception, 7-bit Address) ........ 103 I²C Master Mode (Transmission,

• 7 or 10-bit Address) ........ 102

• I²C Slave Mode (Transmission, 10-bit Address) ........ 89

• I²C Slave Mode (Transmission, 7-bit Address) ........ 87 I²C Slave Mode with SEN = 1 (Reception,

• 10-bit Address) ........ 93 I²C Slave Mode with SEN = 0 (Reception,

• 10-bit Address) ........ 88 I²C Slave Mode with SEN = 0 (Reception,

• 7-bit Address) ........ 86 I²C Slave Mode with SEN = 1 (Reception,

• 7-bit Address) ........ 92

• Parallel Slave Port (PIC16F874A/877A Only) ........ 187

• Parallel Slave Port (PSP) Read ........ 52

• Parallel Slave Port (PSP) Write ........ 52

• Repeat Start Condition ........ 100 Reset, Watchdog Timer, Start-up Timer

• and Power-up Timer ........ 184 Slave Mode General Call Address Sequence

• (7 or 10-bit Address Mode) ........ 94

• Slave Synchronization ........ 77 Slow Rise Time (MCLR Tied to VDD via

• RC Network) ........ 152

• SPI Master Mode (CKE = 0, SMP = 0) ........ 188

• SPI Master Mode (CKE = 1, SMP = 1) ........ 188

• SPI Mode (Master Mode) ........ 76

• SPI Mode (Slave Mode with CKE = 0) ........ 78

• SPI Mode (Slave Mode with CKE = 1) ........ 78

• SPI Slave Mode (CKE = 0) ........ 189

• SPI Slave Mode (CKE = 1) ........ 189

• Stop Condition Receive or Transmit Mode ........ 104 Synchronous Reception

• (Master Mode, SREN) ........ 124

• Synchronous Transmission ........ 122

• Synchronous Transmission (Through TXEN) ........ 122 Time-out Sequence on Power-up
  (MCLR Not Tied to VDD)

• Case 1 ........ 152

• Case 2 ........ 152 Time-out Sequence on Power-up (MCLR Tied

• to VDD via RC Network) ........ 151

• Timer0 and Timer1 External Clock ........ 185 USART Synchronous Receive

• (Master/Slave) ........ 193 USART Synchronous Transmission

• (Master/Slave) ........ 193

• Wake-up from Sleep via Interrupt ........ 157

• Timing Parameter Symbology ........ 181

• TMR0 Register ........ 19

• TMR1CS Bit ........ 57

• TMR1H Register ........ 19

• TMR1L Register ........ 19

• TMR1ON Bit ........ 57

• TMR2 Register ........ 19

• TMR2ON Bit ........ 61

• TMRO Register ........ 21

• TOUTPS0 Bit ........ 61

• TOUTPS1 Bit ........ 61

• TOUTPS2 Bit ........ 61

• TOUTPS3 Bit ........ 61

• TRISA Register ........ 20

• TRISB Register ........ 20

• TRISC Register ........ 20

• TRISD Register ........ 20

• TRISE Register ........ 20

• IBF Bit ........ 50

• IBOV Bit ........ 50

• OBF Bit ........ 50

• PSPMODE Bit ........ 48, 49, 50, 51

• TXREG Register ........ 19

• TXSTA Register ........ 20

• BRGH Bit ........ 111

• CSRC Bit ........ 111

• SYNC Bit ........ 111

• TRMT Bit ........ 111

• TX9 Bit ........ 111

• TX9D Bit ........ 111

• TXEN Bit ........ 111

U

• USART ........ 111
• Address Detect Enable (ADDEN Bit) ........ 112
• Asynchronous Mode ........ 115
• Asynchronous Receive (9-bit Mode) ........ 119 Asynchronous Receive with Address Detect.
  See Asynchronous Receive (9-bit Mode).
• Asynchronous Receiver ........ 117
• Asynchronous Reception ........ 118
• Asynchronous Transmitter ........ 115
• Baud Rate Generator (BRG) ........ 113
• Baud Rate Formula ........ 113 Baud Rates, Asynchronous Mode
• (BRGH = 0) ........ 114 Baud Rates, Asynchronous Mode
• (BRGH = 1) ........ 114
• High Baud Rate Select (BRGH Bit) ........ 111
• Sampling ........ 113
• Clock Source Select (CSRC Bit) ........ 111
• Continuous Receive Enable (CREN Bit) ........ 112
• Framing Error (FERR Bit) ........ 112
• Mode Select (SYNC Bit) ........ 111
• Overrun Error (OERR Bit) ........ 112
• Receive Data, 9th Bit (RX9D Bit) ........ 112
• Receive Enable, 9-bit (RX9 Bit) ........ 112
• Serial Port Enable (SPEN Bit) ........ 111, 112
• Single Receive Enable (SREN Bit) ........ 112
• Synchronous Master Mode ........ 121
• Synchronous Master Reception ........ 123
• Synchronous Master Transmission ........ 121
• Synchronous Slave Mode ........ 124
• Synchronous Slave Reception ........ 125
• Synchronous Slave Transmit ........ 124
• Transmit Data, 9th Bit (TX9D) ........ 111
• Transmit Enable (TXEN Bit) ........ 111
• Transmit Enable, 9-bit (TX9 Bit) ........ 111
• Transmit Shift Register Status (TRMT Bit) ........ 111
• USART Synchronous Receive Requirements ........ 193

V

• VDD Pin ........ 9, 13
• Voltage Reference Specifications ........ 180
• Vss Pin ........ 9, 13

W

• Wake-up from Sleep ........ 143, 156
• Interrupts ........ 149, 150
• MCLR Reset ........ 150
• WDT Reset ........ 150
• Wake-up Using Interrupts ........ 156 Watchdog Timer
• Register Summary ........ 155
• Watchdog Timer (WDT) ........ 143, 155
• Enable (WDTE Bit) ........ 155 Postscaler. See Postscaler, WDT.
• Programming Considerations ........ 155
• RC Oscillator ........ 155
• Time-out Period ........ 155
• WDT Reset, Normal Operation ........ 147, 149, 150
• WDT Reset, Sleep ........ 147, 149, 150
• WCOL ........ 99, 101, 104
• WCOL Status Flag ........ 99
• WWW, On-Line Support ........ 4

DS39582C-page 228 © 2001-2013 Microchip Technology Inc.

THE MICROCHIP WEB SITE

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Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at: http://microchip.com/support

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

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Application (optional): Would you like a reply? ___ Y ___ N Device: PIC16F87XA Literature Number: DS39582C

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DS39582C-page 230 © 2001-2013 Microchip Technology Inc.

PIC16F87XA PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device

PIC16F87XA⁽¹⁾, PIC16F87XAT⁽²⁾; VDD range 4.0V to 5.5V
PIC16LF87XA⁽¹⁾, PIC16LF87XAT⁽²⁾; VDD range 2.0V to 5.5V

Temperature Range

I = -40°C to +85°C (Industrial)

Package

ML = QFN (Metal Lead Frame)
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny Plastic DIP
P = PDIP
L = PLCC
S = SSOP

Examples:

a) PIC16F873A-I/P 301 = Industrial temp., PDIP package, normal VDD limits, QTP pattern #301.
b) PIC16LF876A-I/SO = Industrial temp., SOIC package, Extended VDD limits.
c) PIC16F877A-I/P = Industrial temp., PDIP package, 10 MHz, normal VDD limits.

Note

1: F = CMOS Flash
LF = Low-Power CMOS Flash
2: T = in tape and reel - SOIC, PLCC, TQFP packages only

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC$^{32}$ logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2001-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 9781620769621

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949 =

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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Tel: 66-2-694-1351
Fax: 66-2-694-1350

EUROPE

Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393

Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829

France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79

Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44

Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781

Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340

Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91

UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820

11/29/12