Microchip PIC16 datasheet

28/40/44-Pin Enhanced Flash Microcontrollers

Devices Included in this Data Sheet:

• PIC16F873A
• PIC16F874A
• PIC16F876A
• PIC16F877A

High-Performance RISC CPU:

• Only 35 single-word instructions to learn
• All single-cycle instructions except for program branches, which are two-cycle
• Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle
• Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data Memory (RAM), Up to 256 x 8 bytes of EEPROM Data Memory
• Pinout compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXXX microcontrollers

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler, can be incremented during Sleep via external crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
• Two Capture, Compare, PWM modules
  • Capture is 16-bit, max. resolution is 12.5 ns
  • Compare is 16-bit, max. resolution is 200 ns
  • PWM max. resolution is 10-bit
• Synchronous Serial Port (SSP) with SPI (Master mode) and I²C™ (Master/Slave)
• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection
• Parallel Slave Port (PSP) – 8 bits wide with external RD, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for Brown-out Reset (BOR)

Analog Features:

• 10-bit, up to 8-channel Analog-to-Digital Converter (A/D)
• Brown-out Reset (BOR)
• Analog Comparator module with:
  • Two analog comparators
  • Programmable on-chip voltage reference (VREF) module
  • Programmable input multiplexing from device inputs and internal voltage reference
  • Comparator outputs are externally accessible

Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced Flash program memory typical
• 1,000,000 erase/write cycle Data EEPROM memory typical
• Data EEPROM Retention > 40 years
• Self-reprogrammable under software control
• In-Circuit Serial Programming™ (ICSP™) via two pins
• Single-supply 5V In-Circuit Serial Programming
• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
• Programmable code protection
• Power saving Sleep mode
• Selectable oscillator options
• In-Circuit Debug (ICD) via two pins

CMOS Technology:

• Low-power, high-speed Flash/EEPROM technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low-power consumption

Pin Diagrams

28-Pin PDIP, SOIC, SSOP

MCLR/VPP → 1 ○ 28 ← RB7/PGD RA0/AN0 ← 2 27 ← RB6/PGC RA1/AN1 ← 3 26 ← RB5 RA2/AN2/VREF-/CVREF ← 4 25 ← RB4 RA3/AN3/VREF+ ← 5 24 ← RB3/PGM RA4/T0CKI/C1OUT ← 6 23 ← RB2 RA5/AN4/SS/C2OUT ← 7 22 ← RB1 Vss ← 8 21 ← RB0/INT OSC1/CLKI ← 9 20 ← VDD OSC2/CLKO ← 10 19 ← Vss RC0/T1OSO/T1CKI ← 11 18 ← RC7/RX/DT RC1/T1OSI/CCP2 ← 12 17 ← RC6/TX/CK RC2/CCP1 ← 13 16 ← RC5/SDO RC3/SCK/SCL ← 14 15 ← RC4/SDI/SDA

28-Pin QFN

RA1/AN1 ↑ 28 ○ 21 ← RB3/PGM RA0/AN0 ↑ 27 20 ← RB2 MCLR/Vpp ↓ 26 19 ← RB1 RB7/PGD ↑ 25 18 ← RB0/INT RB6/PGC ↑ 24 17 ← VDD RB5 ↑ 23 16 ← Vss RB4 ↑ 22 15 ← RC7/RX/DT

RA2/AN2/VREF-/CVREF ← 1 14 ← RC6/TX/CK RA3/AN3/VREF+ ← 2 13 ← RC5/SDO RA4/T0CKI/C1OUT ← 3 12 ← RC4/SDI/SDA RA5/AN4/SS/C2OUT ← 4 11 ← RC3/SCK/SCL Vss ← 5 10 ← RC2/CCP1 OSC1/CLKI ← 6 9 ← RC1/T1OSI/CCP2 OSC2/CLKO ← 7 8 ← RC0/T1OSO/T1CKI

44-Pin QFN

RC7/RX/DT ← 1 ● 44 ← RC6/TX/CK RD4/PSP4 ← 2 43 ← RC5/SDO RD5/PSP5 ← 3 42 ← RC4/SDI/SDA RD6/PSP6 ← 4 41 ← RD3/PSP3 RD7/PSP7 ← 5 40 ← RD2/PSP2 Vss ← 6 39 ← RD1/PSP1 VDD ← 7 38 ← RD0/PSP0 VDD ← 8 37 ← RC3/SCK/SCL RB0/INT ← 9 36 ← RC2/CCP1 RB1 ← 10 35 ← RC1/T1OSI/CCP2 RB2 ← 11 34 ← RC0/T1OSO/T1CKI

RB3/PGM ↑ 12 33 → OSC2/CLKO NC ↑ 13 32 → OSC1/CLKI RB4 ↑ 14 31 → Vss RB5 ↑ 15 30 → Vss RB6/PGC ↑ 16 29 → VDD RB7/PGD ↑ 17 28 → VDD MCLR/Vpp ↑ 18 27 → RE2/CS/AN7 RA0/AN0 ↑ 19 26 → RE1/WR/AN6 RA1/AN1 ↑ 20 25 → RE0/RD/AN5 RA2/AN2/VREF-/CVREF ↑ 21 24 → RA5/AN4/SS/C2OUT RA3/AN3/VREF+ ↑ 22 23 → RA4/T0CKI/C1OUT

Pin Diagrams (Continued)

40-Pin PDIP

MCLR/VPP \rightarrow 1 RA0/AN0 \leftrightarrow 2 RA1/AN1 \leftrightarrow 3 RA2/AN2/VREF-/CVREF \leftrightarrow 4 RA3/AN3/VREF+ \leftrightarrow 5 RA4/T0CKI/C1OUT \leftrightarrow 6 RA5/AN4/SS/C2OUT \leftrightarrow 7 RE0/RD/AN5 \leftrightarrow 8 RE1/WR/AN6 \leftrightarrow 9 RE2/CS/AN7 \leftrightarrow 10 VDD \rightarrow 11 VSS \leftarrow 12 OSC1/CLKI \leftarrow 13 OSC2/CLKO \rightarrow 14 RC0/T1OSO/T1CKI \leftrightarrow 15 RC1/T1OSI/CCP2 \leftrightarrow 16 RC2/CCP1 \leftrightarrow 17 RC3/SCK/SCL \leftrightarrow 18 RD0/PSP0 \leftrightarrow 19 RD1/PSP1 \leftrightarrow 20

PIC16F874A/877A

40 \leftarrow RB7/PGD 39 \leftarrow RB6/PGC 38 \leftarrow RB5 37 \leftarrow RB4 36 \leftarrow RB3/PGM 35 \leftarrow RB2 34 \leftarrow RB1 33 \leftarrow RB0/INT 32 \leftarrow VDD 31 \leftarrow VSS 30 \leftarrow RD7/PSP7 29 \leftarrow RD6/PSP6 28 \leftarrow RD5/PSP5 27 \leftarrow RD4/PSP4 26 \leftarrow RC7/RX/DT 25 \leftarrow RC6/TX/CK 24 \leftarrow RC5/SDO 23 \leftarrow RC4/SDI/SDA 22 \leftarrow RD3/PSP3 21 \leftarrow RD2/PSP2

44-Pin PLCC

RA4/T0CKI/C1OUT \leftrightarrow 7 RA5/AN4/SS/C2OUT \leftrightarrow 8 RE0/RD/AN5 \leftrightarrow 9 RE1/WR/AN6 \leftrightarrow 10 RE2/CS/AN7 \leftrightarrow 11 VDD \rightarrow 12 VSS \leftarrow 13 OSC1/CLKI \leftarrow 14 OSC2/CLKO \rightarrow 15 RC0/T1OSO/T1CKI \leftrightarrow 16 NC \leftrightarrow 17

PIC16F874A PIC16F877A

RA3/AN3/VREF+ \updownarrow 6 RA2/AN2/VREF-/CVREF \updownarrow 5 RA1/AN1 \updownarrow 4 RA0/AN0 \updownarrow 3 MCLR/VPP \downarrow 2 NC \downarrow 1 RB7/PGD \updownarrow 44 RB6/PGC \updownarrow 43 RB5 \updownarrow 42 RB4 \updownarrow 41 NC \updownarrow 40

39 \leftarrow RB3/PGM 38 \leftarrow RB2 37 \leftarrow RB1 36 \leftarrow RB0/INT 35 \leftarrow VDD 34 \leftarrow VSS 33 \leftarrow RD7/PSP7 32 \leftarrow RD6/PSP6 31 \leftarrow RD5/PSP5 30 \leftarrow RD4/PSP4 29 \leftarrow RC7/RX/DT

RC1/T1OSI/CCP2 \updownarrow 18 RC2/CCP1 \updownarrow 19 RC3/SCK/SCL \updownarrow 20 RD0/PSP0 \updownarrow 21 RD1/PSP1 \updownarrow 22 RD2/PSP2 \updownarrow 23 RD3/PSP3 \updownarrow 24 RC4/SDI/SDA \updownarrow 25 RC5/SDO \updownarrow 26 RC6/TX/CK \updownarrow 27 NC \updownarrow 28

44-Pin TQFP

RC7/RX/DT \leftrightarrow 1 RD4/PSP4 \leftrightarrow 2 RD5/PSP5 \leftrightarrow 3 RD6/PSP6 \leftrightarrow 4 RD7/PSP7 \leftrightarrow 5 VSS \leftarrow 6 VDD \rightarrow 7 RB0/INT \leftrightarrow 8 RB1 \leftrightarrow 9 RB2 \leftrightarrow 10 RB3/PGM \leftrightarrow 11

PIC16F874A PIC16F877A

RC6/TX/CK \uparrow 44 RC5/SDO \uparrow 43 RC4/SDI/SDA \uparrow 42 RD3/PSP3 \uparrow 41 RD2/PSP2 \uparrow 40 RD1/PSP1 \uparrow 39 RD0/PSP0 \uparrow 38 RC3/SCK/SCL \uparrow 37 RC2/CCP1 \uparrow 36 RC1/T1OSI/CCP2 \uparrow 35 NC \uparrow 34

NC \leftarrow 33 RC0/T1OSO/T1CKI \leftrightarrow 32 OSC2/CLKO \rightarrow 31 OSC1/CLKI \leftarrow 30 VSS \leftarrow 29 VDD \rightarrow 28 RE2/CS/AN7 \leftrightarrow 27 RE1/WR/AN6 \leftrightarrow 26 RE0/RD/AN5 \leftrightarrow 25 RA5/AN4/SS/C2OUT \leftrightarrow 24 RA4/T0CKI/C1OUT \leftrightarrow 23

NC \updownarrow 12 NC \updownarrow 13 RB5 \updownarrow 14 RB6/PGC \updownarrow 15 RB7/PGD \updownarrow 16 MCLR/VPP \downarrow 17 RA0/AN0 \updownarrow 18 RA1/AN1 \updownarrow 19 RA2/AN2/VREF-/CVREF \updownarrow 20 RA3/AN3/VREF+ \updownarrow 21

Table of Contents

• 1.0 Device Overview ........ 5
• 2.0 Memory Organization ........ 15
• 3.0 Data EEPROM and Flash Program Memory ........ 33
• 4.0 I/O Ports ........ 41
• 5.0 Timer0 Module ........ 53
• 6.0 Timer1 Module ........ 57
• 7.0 Timer2 Module ........ 61
• 8.0 Capture/Compare/PWM Modules ........ 63
• 9.0 Master Synchronous Serial Port (MSSP) Module ........ 71
• 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........ 111
• 11.0 Analog-to-Digital Converter (A/D) Module ........ 127
• 12.0 Comparator Module ........ 135
• 13.0 Comparator Voltage Reference Module ........ 141
• 14.0 Special Features of the CPU ........ 143
• 15.0 Instruction Set Summary ........ 159
• 16.0 Development Support ........ 167
• 17.0 Electrical Characteristics ........ 173
• 18.0 DC and AC Characteristics Graphs and Tables ........ 197
• 19.0 Packaging Information ........ 209
• Appendix A: Revision History ........ 219
• Appendix B: Device Differences ........ 219
• Appendix C: Conversion Considerations ........ 220
• Index ........ 221
• On-Line Support ........ 229
• Systems Information and Upgrade Hot Line ........ 229
• Reader Response ........ 230
• PIC16F87XA Product Identification System ........ 231

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1.0 DEVICE OVERVIEW

This document contains device specific information about the following devices:

• PIC16F873A
• PIC16F874A
• PIC16F876A
• PIC16F877A

PIC16F873A/876A devices are available only in 28-pin packages, while PIC16F874A/877A devices are available in 40-pin and 44-pin packages. All devices in the PIC16F87XA family share common architecture with the following differences:

• The PIC16F873A and PIC16F874A have one-half of the total on-chip memory of the PIC16F876A and PIC16F877A
• The 28-pin devices have three I/O ports, while the 40/44-pin devices have five
• The 28-pin devices have fourteen interrupts, while the 40/44-pin devices have fifteen
• The 28-pin devices have five A/D input channels, while the 40/44-pin devices have eight
• The Parallel Slave Port is implemented only on the 40/44-pin devices

The available features are summarized in Table 1-1. Block diagrams of the PIC16F873A/876A and PIC16F874A/877A devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts for these device families are listed in Table 1-2 and Table 1-3.

Additional information may be found in the PIC® Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.

TABLE 1-1: PIC16F87XA DEVICE FEATURES

FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM

Note 1: Higher order bits are from the Status register.

FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM

Note 1: Higher order bits are from the Status register.

TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION

Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED)

Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION

Legend: I = input O = output I/O = input/output P = power— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

DS39582C-page 10 © 2001-2013 Microchip Technology Inc.

TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)

Legend:
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
Note 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)

Legend: I = input O = output I/O = input/output P = power— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

DS39582C-page 12 © 2001-2013 Microchip Technology Inc.

TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)

Legend: I = input O = output I/O = input/output P = power— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

NOTES:

DS39582C-page 14 © 2001-2013 Microchip Technology Inc.

2.0 MEMORY ORGANIZATION

There are three memory blocks in each of the PIC16F87XA devices. The program memory and data memory have separate buses so that concurrent access can occur and is detailed in this section. The EEPROM data memory block is detailed in Section 3.0 "Data EEPROM and Flash Program Memory".

Additional information on device memory may be found in the PIC® Mid-Range MCU Family Reference Manual (DS33023).

2.1 Program Memory Organization

The PIC16F87XA devices have a 13-bit program counter capable of addressing an 8K word x 14 bit program memory space. The PIC16F876A/877A devices have 8K words x 14 bits of Flash program memory, while PIC16F873A/874A devices have 4K words x 14 bits. Accessing a location above the physically implemented address will cause a wraparound.

The Reset vector is at 0000h and the interrupt vector is at 0004h.

FIGURE 2-1: PIC16F876A/877A PROGRAM MEMORY MAP AND STACK

FIGURE 2-2: PIC16F873A/874A PROGRAM MEMORY MAP AND STACK

2.2 Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (Status<6>) and RP0 (Status<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access.

Note: The EEPROM data memory description can be found in Section 3.0 “Data EEPROM and Flash Program Memory” of this data sheet.

2.2.1 GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indirectly, through the File Select Register (FSR).

FIGURE 2-3: PIC16F876A/877A REGISTER FILE MAP

• Unimplemented data memory locations, read as ‘0’.
• • Not a physical register.
• Note 1: These registers are not implemented on the PIC16F876A.
• Note 2: These registers are reserved; maintain these registers clear.

FIGURE 2-4: PIC16F873A/874A REGISTER FILE MAP

• Unimplemented data memory locations, read as ‘0’.
• • Not a physical register.
• Note 1: These registers are not implemented on the PIC16F873A.
• Note 2: These registers are reserved; maintain these registers clear.

DS39582C-page 18 © 2001-2013 Microchip Technology Inc.

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1.

The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral features section.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.

2.2.2.1 Status Register

The Status register contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory.

The Status register can be the destination for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the \overlineTO and \overlinePD bits are not writable, therefore, the result of an instruction with the Status register as destination may be different than intended.

For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status register because these instructions do not affect the Z, C or DC bits from the Status register. For other instructions not affecting any status bits, see Section 15.0 "Instruction Set Summary".

Note: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

\begin{tabular}{lllllllll} R/W-0 & R/W-0 & R/W-0 & R-1 & R-1 & R/W-x & R/W-x & R/W-x \ IRP & RP1 & RP0 & \overlineTO & \overlinePD & Z & DC & C \ bit 7 & & & & & & & bit 0 \ \end{tabular}

bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) Each bank is 128 bytes.

bit 4 \overlineTO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

bit 3 \overlinePD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high, or low order bit of the source register.

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

• n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

2.2.2.2 OPTION_REG Register

The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.

REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)

bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKO)

bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

2.2.2.3 INTCON Register

The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software). 0 = None of the RB7:RB4 pins have changed state

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

• n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

DS39582C-page 24 © 2001-2013 Microchip Technology Inc.

2.2.2.4 PIE1 Register

The PIE1 register contains the individual enable bits for the peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.

REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)

bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit⁽¹⁾
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt

Note 1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear.

bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt

bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt

bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt

bit 3
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt

bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’

• n = Value at POR
  ‘1’ = Bit is set
  ‘0’ = Bit is cleared
  x = Bit is unknown

2.2.2.5 PIR1 Register

The PIR1 register contains the individual flag bits for the peripheral interrupts.

Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.

REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)

bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred

Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear.

bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete

bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty

bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full

bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are:

• SPI – A transmission/reception has taken place.
• I²C Slave – A transmission/reception has taken place.
• I²C Master
  • A transmission/reception has taken place.
  • The initiated Start condition was completed by the SSP module.
  • The initiated Stop condition was completed by the SSP module.
  • The initiated Restart condition was completed by the SSP module.
  • The initiated Acknowledge condition was completed by the SSP module.
  • A Start condition occurred while the SSP module was Idle (multi-master system).
  • A Stop condition occurred while the SSP module was Idle (multi-master system).
    0 = No SSP interrupt condition has occurred

bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM mode:
Unused in this mode.

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

2.2.2.6 PIE2 Register

The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt and the comparator interrupt.

Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.

REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)

bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disable the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enable EEPROM write interrupt 0 = Disable EEPROM write interrupt bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enable bus collision interrupt 0 = Disable bus collision interrupt bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

• n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

2.2.2.7 PIR2 Register

The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt and the comparator interrupt.

Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)

• bit 7 Unimplemented: Read as ‘0’
• bit 6 CMIF: Comparator Interrupt Flag bit
  • 1 = The comparator input has changed (must be cleared in software)
  • 0 = The comparator input has not changed
• bit 5 Unimplemented: Read as ‘0’
• bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
  • 1 = The write operation completed (must be cleared in software)
  • 0 = The write operation is not complete or has not been started
• bit 3 BCLIF: Bus Collision Interrupt Flag bit
  • 1 = A bus collision has occurred in the SSP when configured for I²C Master mode
  • 0 = No bus collision has occurred
• bit 2-1 Unimplemented: Read as ‘0’
• bit 0 CCP2IF: CCP2 Interrupt Flag bit
  • Capture mode:
    • 1 = A TMR1 register capture occurred (must be cleared in software)
    • 0 = No TMR1 register capture occurred
  • Compare mode:
    • 1 = A TMR1 register compare match occurred (must be cleared in software)
    • 0 = No TMR1 register compare match occurred
  • PWM mode:
    • Unused.

Legend:

• R = Readable bit
• W = Writable bit
• U = Unimplemented bit, read as ‘0’
• • n = Value at POR
• ‘1’ = Bit is set
• ‘0’ = Bit is cleared
• x = Bit is unknown

2.2.2.8 PCON Register

The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset.

Note: \overlineBOR is unknown on Power-on Reset. It must be set by the user and checked on subsequent Resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a “don’t care” and is not predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the configuration word).

REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)

bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 \overlineBOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

• n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any Reset, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-5: LOADING OF PC IN DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the application note, AN556, “Implementing a Table Read” (DS00556).

2.3.2 STACK

The PIC16F87XA family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POP’ed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

Note 1: There are no status bits to indicate stack overflow or stack underflow conditions.

2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.

2.4 Program Memory Paging

All PIC16F87XA devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the RETURN instructions (which POPs the address from the stack).

Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions.

Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).

EXAMPLE 2-1: CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0

ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 ;Select page 1 ; (800h-FFFh) CALL SUB1_P1 ;Call subroutine in : ;page 1 (800h-FFFh) : ORG 0x900 ;page 1 (800h-FFFh) SUB1_P1 : ;called subroutine ;page 1 (800h-FFFh) : RETURN ;return to ;Call subroutine ;in page 0 ; (000h-7FFh)

2.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0) will read 00h. Writing to the INDF register indirectly results in a no operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (Status<7>) as shown in Figure 2-6.

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: INDIRECT ADDRESSING MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM NEXT CLRF INDF ;clear INDF register INCF FSR,F ;inc pointer BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next CONTINUE : ;yes continue

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING

Note 1: For register file map detail, see Figure 2-3.

NOTES: