i got a board build around samsung's S3C2410 ( might be 2410a, i am not pretty sure ) which in turn build on ARM920T core.
Both in ARM920T's specification and S3C210's specification, i get know the processor core has seperated 16k 64-way set-association data cache and instruction cache. but, in the /proc/cpuinfo, i see,
Processor : ARM/CIRRUS Arm920Tsid(wb) rev 0 (v4l) BogoMIPS : 99.94 Features : swp half thumb CPU implementor : 0x41 CPU architecture: 4T CPU variant : 0x1 CPU part : 0x920 CPU revision : 0 Cache type : write-back Cache clean : cp15 c7 ops Cache lockdown : format A Cache unified : harvard I size : 8192 I assoc : 32 I line length : 32 I sets : 8 D size : 8192 D assoc : 32 D line length : 32 D sets : 8
the info above indicates that the instruction cache and data cache is
8k 32-way set-association. i am wondering which information is right? and, how the linux generated the cpuinfo file?thanks.
- woody