Re: Machine hangs when writing in battery backed SRAM

Hi,

Sorry for not being an expert in the x86 architecture, but in the 68K world the above doesn't sound too unfamilar to me. So let's gimme a shot in the dark:

How are the MMU settings for the "memory hole"? Is the physical address the SDRAM is mapped into marked as cachable? The CPU will not write out data immediately, it will buffer it as long as the corresonponding cache lines are available.

What you're doing here seems to me like first writing the data into the cache, then "pulling the rug" under the CPU and let the cache controller write the data into never-never-land. The result is likely an access error or even a bus error, and that's possibly the cause for the hang.

So long, Thomas

corresonponding

The point seems to be exactly this. Apparently I solved the problem setting, in the BIOS parameters, the memory above 1MB as "write through" instead of the original "write back". As far as I could understand, the difference is that write through writes as soon as it can while write back writes only when necessary, i.e. when the hole is closed I presume.

Hi,

That's indeed the case (and matches the wording I'm used to in the MC68K world). Write through means the data goes into the cache, and *immediately* onto the bus on the same time. Write back means the data stays in the cache and remains there until the cache line is needed. Write through will *not* read from memory in case the data is in the cache already. In case your SDRAM can be modified by other means than the CPU, you should disable caching completely (if that's possible; in worst case, the MMU had to be programmed).

So long, Thomas