Hi Everyone
I'm designing a system which uses low power SRAM powered by battery as a backup device. The data sheet states that all I/Os mus be kept within
0.2V of either Vcc or GND for the standby current to be guaranteed. This is no surprise, one CMOS device must be held firmly in the off state.
The I/Os will be connected to a powered down CMOS buffer while in standby mode, and my question is: will the powered down buffer have enough leakage current hold the I/Os at ground potential, or should I provide weak pull-down resistors to prevent these pins from floating above 0.2V?
TIA Cheers Geoff