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Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)

First of all, the document you referenced does NOT contain any more information than the one I've referenced. It's just an older version of the document I have referenced, and since I am using the newer version of the core, that is the version of the document I'm looking at.

Second, since obviously not everyone here knows enough about binary arithmetics to understand my questions, let me illustrate on an example of adding/subtracting 2 3-bit signed numbers:

Using 2's complement representation, we can represent the following numbers with 3 bits:

0 = 000 1 = 001 2 = 010 3 = 011

-4 =100

-3 =101

-2 =110

-1 =111

What is the lowest result we can get by adding/subtracting two 3-bit signed numbers? Obviously:

-4 + -4 = 100

  • 100 =1000 = (-8 if all 4 bits are considered, or 0 if only 3 bits are considered)

To store the valid result, we only need 4 bits.

What is the highest number we can get by adding/subtracting two 3-bit signed numbers? Obvioulsy:

3+3 = 011
  • 011 = 0110 (6 if all 4 bits are considered, otherwise -2 if only 3 bits are considered)

To store the valid result we again need at most 4 bits.

Now let's go with the terminology in the Core specification

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): N=2, M=2 (because both numbers are three bits wide, so the range of indices is 2:0). Therefore, Q = MAX (N,M) = 2. Now, according to the specification, the result can have width of [Q+1:0], which is [3:0] = 4 bits if both numbers can be signed. This corresponds to my reasoning above.

However, if one of the numbers is unsigned, 4 bits are not enough. We can illustrate that using the following example:

-4 - (7) = -11 If we represent -4 with a 3-bit signed number and 7 with a three bit signed number, we need to sign extend them both (to 4 bits) to be able to get correct result, and we need 5 bits to store the correct result (-11 obviously cannot fit in 4-bits). This explains why P=Q+2 (instead of Q+1) when one of the numbers is unsigned, which was one of my original questions, but nobody would answer it. And I didn't understand it until I performed this analysis.

There, I had to answer one of my questions myself.

However, this still doesn't explain what is the difference between the following two cases:

(See Table 2 in

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to understand what I'm talking about.)

  1. Operand A: Unsigned, Operand B: Signed or by input pin (2nd row), when the input pin is set so that the operand B is signed

and

  1. Operand A: Signed or by input pin, Operand B: Signed or by input pin, (last row) when the input pins denote that the operand A is unsigned and operand B is signed

In both cases 1 and 2 above the operands are exactly the same, but the availability of the overflow flag and the widths of the result are different. In particular, I cannot get the result to be of the width P=Q+2 in case 2. WHY?????????????????????????????????????????

Also, in table 2, why is overflow not available if I select the width of the output to be P=Q+1????

Reply to
juendme
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Slight correction in the above example: "If we represent -4 with a 3-bit signed number and 7 with a three bit signed number.."

should be:

"If we represent -4 with a 3-bit signed number and 7 with a three bit unsigned number.."

Reply to
juendme

Fred,

OK, so I used an older version, it also happens to be online, and it also has a misprint for the figure number. Got that straight now.

I don't really know the answer to your questions that you ask below (disregarding that you figured out the answer to your first question yourself). But read on:

-snip-

No, one case is signed/signed (2.), and the other is unsigned/signed (1.).

but the

I'll let someone else puzzle this out, but it also may be because that is the way the core is written (it is just what it does). And it also seems logical that if an overflow can not occur, then no overflow bit is required (the output has enough bits).

Anyone?

Austin

Reply to
Austin Lesea

This could have been en enlightening discussion, if the OP had avoided the confrontational, accusatory tone. Horror over horrors, he had not gotten an answer by Monday for a question that he had asked on Thursday. That's 2 business days... Does that justify a flamethrower attack?

Peter Alfke

Reply to
Peter Alfke

So, there are 2 pins, A_SIGNED and B_SIGNED, and I set them so that it is unsigned/signed, just like in case 1.

Reply to
juendme

It can still be an enlightening discussion. My accusatory tone is in response to the overall poor quality of Xilinx documentation. Besides, shouldn't the attitude be: The customer is always right?

The problem is not that I didn't get the answer fast. The problem is that everyone is so smart in giving advice to the questions that have not been asked. When I don't know the answer to some question, I don't reply to the topic.

However, many people seem to want to be smart and say something, regardless of the fact that I explicitly said that I don't need those answers. I find that annoying.

I might have not been clear in the beginning in terms of what my question was, but later I clarified, and I still got responses that answer the questions I didn't ask.

Regards,

Fred

Reply to
juendme

Fred, this is a public newsgroup. Answers are posted voluntarily and for free. Only a few of us are employed by companies that have a stake in this, and benefit more or less directly from the timely resolution of apparent problems (I fall into this latter category). That's why it is so important to maintain a friendly and cooperative spirit, and avoid insults and slamming. If you feel that Xilinx documentation is not perfect, I would be the first to agree. But similar critique can also be voiced about lots of other documentation. FPGAs are being used by a wide variety of designers with widely varying background and expertise. It is tough enough to avoid mistakes, even tougher to be complete, and hopeless to please everybody. Let's be friendly and cooperative, and avoid insults... Peter

Reply to
Peter Alfke

[...]

Clearly if you add two sign bits together, you can store the result in ... one sign bit.

And the surprise of this is ... ?

- Brian

Reply to
Brian Drummond

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