Why won't Xilinx document their code??

Question

If I look at your latest unisim_vital.vhd and the previous version of the file, there have been some major changes that effected my simulation. Interesting, once again the headers did not change. They still show the file not being updated after 1996, ending with change

I brought this up with the models in the past.

Is there a reason that you don't want to take the time to document your work?

Ray Andraka · Accepted Answer

Probably in a related vein, Xilinx has removed the TimingChecksOn genericfrom the clocked elements in the unisim library.  Not a problem if younever touched it, however the default value had been true, which createdsome delta clock delay problems with mixed instantiated/inferred designsa while back.  As a result, my library, and I'm sure others has elementswith these primitives with the TimingChecksOn generic set to false.  Nowwith the new unisim library, it is completely gone, so any old code hasto be revised to be able to compile.  Would have been much cleaner tojust leave the generic there as a dummy, even if it has no references inthe component.lecroy wrote:----Ray Andraka, P.E.President, the Andraka Consulting Group, Inc.401/884-7930     Fax 401/884-7950email  "They that give up essential liberty to obtain a little  temporary safety deserve neither liberty nor safety."                                          -Benjamin Franklin, 1759

Why won't Xilinx document their code??

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