VHDL language is out of date! Why? I will explain.

psihodelia · 2007-11-16T18:27:59+00:00

Just look at its syntax. It is so archaic that anyone who had any dealwith Python will just laugh. Try, say, to create a simple VGAcontroller, which is simply readable.VHDL's Ada syntax is also very error prone. Instead of having all thisarchaic constructions and surplus operators, it would be much moreproductive just to start thinking about to create another hi-level HDLthat has absolutely another conceptual design and simple syntax.Any good language should be so simple as possible and any program inthis language should be short and clear. Such language should supportassociative arrays, that should help designing large FSMs; shouldsupport simple mechanism of type conversions and so on...Conceptually VHDL is not bad at all, it supports a lot of things, wellin theory. But in praxis ...And don't forget about future FPGAs, about future SoCs, which willhave integrated MEMS arrays, and other stuff. Try to understand howmuch complexer they are to be designed in so unproductive way using soprimitive languages.

Nov 16, 2007 41 Replies

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Jan Decaluwe 18 years ago

Has been done, with an example from Xilinx itself:

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Note that for synthesis, MyHDL *relies* on a Verilog/VHDL design flow. Synthesis results will thus be similar, obviously.

Jan

Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com

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MikeShepherd564 18 years ago

Don't propound. We're just artisans here, not philosophers. We all have notions of how certain things might be done better, but this group is for practical problems, not for changing the world.

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