Indeed. Altera recommends using the reset async port but with sync signal pre-synchronised. Xilinx, I believe, recommends using synchronous sync. But again we need to be careful about our wording. Synchronous sync is actually applied to input D through logic and does not mean necessarily it is pre-synchronised. Whether you name it async or sync, the signal be default is not pre-synchronised and for sake of timing at release, they have to be generated from flip's clock domain before applying it.
With today's large designs I prefer not to apply reset unless absolutely needed. I know many of us will apply it as routine to masses of buses at every node but I believe it puts massive burden on fitter to meet removal/recovery timing when such effort better be directed somewhere more critical.
Kaz
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