5 years ago
I've gone over to doing it almost universally for C++ development,
because It Just Works -- you lengthen the time to integration a bit, but
vastly shorten the actual integration time.
I did a web search and didn't find it mentioned -- the traditional "make
a test bench" is part way there, but as presented in my textbook* doesn't
impose a comprehensive suite of tests on each module.
So is no one doing it, or does it have another name, or an equivalent
design process with a different name, or what?
* "The Verilog Hardware Description Language", Thomas & Moorby, Kluwer,