SystemC to Verilog Translator v0.4

Feb 28, 2005 0 Replies

OpenSoc has released a new version of his free SystemC to Verilog Synthesizable Subset Translator with new features like function translation support.



You can download it from

formatting link



Best Regards



Javier Castillo snipped-for-privacy@opensocdesign.com

formatting link


Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required