One engineering rule is that "there is no such thing a digital". You seem to understand that. Digital logic is just a simplification of analog electronics used well away from thresholds. But another, more subtile rule is that "there is no such thing as analog". At 10e-22 seconds you are closer to the limits of electrical and thermal noise, maybe even quantum uncertainty. Neither standard Spice, nor an event-driven simulator will do. You will need do a statistical analysis.
So you need to define "reliable" at some statistical level. Before throwing out a long string of nine's for your desired synchronizer failure rate, you also might want to ask about thermal noise, ground noise, EMI, crosstalk, environmental and package radiation, latent process faults which passed chip test, solder reliability, etc. etc. and how those might affect your total system failure rates.
IMHO. YMMV.