I really appreciate all the inputs. Here is where I stand today.
We have not yet finished the prototype (got delayed by OLED interface issues, and also explored more creative ways to reduce jitter and wander), but that's now behind us. We generate 2 output channels (since it is almost for free) and have a dual-16 character (really: 128 x 64 pixel) display. We will use a312.5 MHz xtal oscillator that promises single-digit ppm accuracy. For the first dozen prototypes I will ignore the accuracy question, since the average user seems to be content with 20 ppm. But we do not want to remain "average"... We will provide for a calibration input, and also for the non-volatile storage of calibration factors (We already store hundreds of frequencies for recall, again because it is almost for free). Calibration will be by arithmetic number crunching, nothing analog here. We don't change the internal clock frequency, we just change the DDS/PLL interpretation. For the later calibration strategy, we use the fact that we can adjust our signal output to any frequency with 1 Hz granularity. So we can match any comparison frequency "anywhere in the world".
We need a Virtex-5 LXT50 chip, due to the way we (ab)use the GTPs, but that gives us an enormous amount of spare logic, RAMs and multipliers. There is also a chip thermometer with digital read-out on every Virtex-5 die. It really is an embarrassment of riches. And we can fine- tune the design as often as we have time and patience. Aren't FPGAs fun ! Thanks again. I have a few things to read and study. Peter Alfke