Hi, everybody:
I have two similar designs the only difference is filtering(involving registers and logic differences), while the rest are same...Now I P& R them with the same guide file containing the fixed portion...
If I do a bitgen to generate the difference bitstream of these two routed designs, will it work on hardware? The BitGen allows me to generate a 1kb bitstream...while the fixed logic is 100kb+...
The wording in the XAPP290 is "not recomended", but does the contention cause temporarily mulfunction in the logic (which can be recovered with my design) or will the contention burn the FPGA chip?
Thanks for your advice. Kelvin