These last few months, I have been slowly moving back to my main interests, EDA tools (as a developer and as a user), FPGA application engineering, an d last but not least processor design. After a 5-year hiatus I have started revamping (and modernizing) my own environment, developed as an outcome of my PhD work on application-specific instruction-set processors (ASIPs). Th e flow was based on SUIF/Machine-SUIF (compiler), SALTO (assembly-level tra nsformations) and ArchC (architecture description language for producing bi nary tools and simulators). It was a highly-successful flow that allowed me (along with my custom instruction generator YARDstick) to explore configur ations and extensions of processors with seconds or minutes.
I have been thinking about what's next. We have tools to assist the designe r (the processor design engineer per se) to speedup his/her development. St ill, the processor must be designed explicitly. What would go beyond the st ate-of-the-art is not to have to design the golden model of the processor a t all.
What I am proposing is an application-specific processor synthesis tool tha t goes beyond the state-of-the-art. A model generator for producing the hig h-level description of the processor, based only on application analysis an d user-defined constraints. And for the fun of it, let's codename it METATO R, because I tend to watch too much Supernatural these days, and METATOR (m essenger) is a possible meaning for METATRON, an angelic being from the Apo crypha with a human past. So think of METATOR as an upgrade (spiritual or n ot) to the current status of both academic and commercial ASIP design tools .
- The Context, the Problem and its Solution
ASIPs are tuned for cost-effective execution of targeted application sets. An ASIP design flow involves profiling, architecture exploration, generatio n and selection of functionalities and synthesis of the corresponding hardw are while enabling the user taking certain decisions.
The state-of-the-art in ASIP synthesis includes commercial efforts from Syn opsys which has accumulated three relevant portfolios: the ARC configurable processor cores, Processor Designer (previously LISATek) and the IP Design er nML-based tools (previously Target Compiler Technologies); ASIPmeister b y ASIP Solutions (site down?), Lissom/CodAL by Codasip, and the academic TC E and NISC toolsets. Apologies if I have missed any other ASIP technology p rovider!
The key differentiation point of METATOR against existing approaches is tha t ASIP synthesis should not require the explicit definition of a processor model by a human developer. The solution implies the development of a novel scheme for the extraction of a common denominator architectural model from a given set of user applications (accounting for high-level constraints an d requirements) that are intended to be executed on the generated processor by the means of graph similarity extraction. From this automatically gener ated model, an RTL description, verification IP and a programming toolchain would be produced as part of an automated targeting process, in like "meta
-": a generated model generating models!.
- Conceptual ASIP Synthesis Flow
METATOR would accept as input the so-called algorithmic soup (narrow set of applications) and generate the ADL (Architecture Description Language) des cription of the processor. My first aim would be for ArchC but this could a lso expand to the dominant ADLs, LISA 2.0 and nML.
METATOR would rely upon HercuLeS high-level synthesis technology and the YA RDstick profiling and custom instruction generation environment. In the pas t, YARDstick has been used for generating custom instructions (CIs) for Byo RISC (Build Your Own RISC) soft-core processors. ByoRISC is a configurable in-order RISC design, allowing the execution of multiple-input, multiple-ou tput custom instructions and achieving higher performance than typical VLIW architectures. CIs for ByoRISC where generated by YARDstick, which purpose is to perform application analysis on targeted codes, identify application hotspots, extract custom instructions and evaluate their potential impact on code performance for ByoRISC.
- Conclusion
To sum this up, METATOR is a mind experiment in ASIP synthesis technology. It automatically generates a full-fledged processor and toolchain merely fr om its usage intent, expressed as indicative targeted application sets.
Best regards Nikolaos Kavvadias