Re: power saving condition test ?

Sorry, my mistake. I was thinking in a case where another branch exists to
set a = 1. e.g

if (a&b) a <= 0;
else if (c) a <= 1;

is certainly not the same as

if (b) a <= 0;
else if (c) a <= 1;

Anyway, synthesis tools are supposed to remove any redundant terms in
equations. As for the power saving, in CMOS, ideally there shouldn't be
additional power consumption if a doesn't change value.

Jim Wu
snipped-for-privacy@yahoo.com



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