power of two multiplier

Hi, In the error update path of an adaptive filter I am implementing a power of two multiplier; I am converting the full binary error to the next higher magnitude power of two which then gets encoded to a sign and shift count. So the multiplication is a barrel shift and a sign change if necessary. So far this has a trivial verilog implementation but both the RTL and the gate level output reads as if there can be some interesting optimizations. I am currently using a special code to represent errors of exactly zero and a mux after the shifter to generate multiplication by zero. Anyone has done a similar update path or multiplier? Any ideas, tricks which I can use to reduce the critical path/area ?


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