Hello all,
Will an FPGA PLL lock onto a biphase mark(Manchester ??) encoded signal? I'm trying to build an SPDIF receiver and am wondering if its possible to directly connect the input signal(after analog level adjustment) to an FPGA and read the level at the 90 and 270 degree phases. If frames are continuously being transmitted when the PLL attempts to lock on, how does it know which frequency to use? It seems if all zeros are being transmitted the PLL will lock to half the frequency it should.