PLLs on biphase mark signals

Probably not for a Xilinx Virtex II, Spartan III or Virtex II Pro, the FPGA specs state that the DCM inputs must have < 1ns period jitter, outside which they will lose lock. A true-PLL design may be more forgiving, though.

-Jim

possible to

an FPGA

SPDIF is only 48kHz * 32 bits * 2 channels * 2 for biphase = 6MHz Any modern FPGA will do 100MHz easy. So just oversample the signal and decode it like a UART would.

To build a transmitter locked to the receiver would be more difficult. Alan Nishioka snipped-for-privacy@accom.com

possible to

an FPGA

SPDIF is only 48kHz * 32 bits * 2 channels * 2 for biphase = 6MHz Any modern FPGA will do 100MHz easy. So just oversample the signal and decode it like a UART would.

To build a transmitter locked to the receiver would be more difficult. Alan Nishioka snipped-for-privacy@accom.com

A Manhester decoder can be implemented in less than one Virtex-II CLB. You need an 8x oversampling clock, but the tolerances are quite generous: The clock frequency must be between 5 and 12 times the incoming bit rate. Send me an e-mail if you need the code. I described the concept years ago in our XCell magazine.

signal?

possible to

an FPGA

A Manhester decoder can be implemented in less than one Virtex-II CLB. You need an 8x oversampling clock, but the tolerances are quite generous: The clock frequency must be between 5 and 12 times the incoming bit rate. Send me an e-mail if you need the code. I described the concept years ago in our XCell magazine.

Thanks to the responses. I'm gonna have a go at it on my own first and see what I come up with.