IQ modulator

Probably it takes LO at 4 times the frequency and does this 90 degree phase shift using 2 digital flip-flops?

Looks like one has to buy it direct from LT...what kind of rockstar money does it cost?

Possibly. Though I suspect it may be a PLL. ...Jim Thompson

says so right on their page, 1-99, $7.39, 100+ $6.23

They say it's a phase shift network. Dunno how they manage it, tho.

There are IQ modulators that use digital dividers to make the phase shift, but I don't think this one does. I'm guessing it's a linear all-pass, a very good one, possibly with some tricks.

Digikey has it for $11, qty 1.

I need two per roughly $5K box, so it's a bargain. Not that I expect to make money on this thing. This is one of those small-quantity jobs that we're doing as a favor for a good customer. This chip makes it a lot easier. Most IQ modulators start at 100 MHz or more.

Still, it is interesting.

I can probably get a lifetime supply, 8 chips maybe? , as samples.

Why does Digikey want $11?

do

to pay rent? ;)

Finally, you can phaseshift a waveform into the future.

NT

Win Hill knows. AOE 2 - phase sequence network, figure 5.41 on pge 295. In AOE 3 it's figure 7.48 on page 456.

And, it just occurred to me, having done multi-chip clock synchronization _years_ ago... a DLL, delay-locked-loop: voltage-variable digital delay line, phase detector, voila! ...Jim Thompson

The suggested accompanying VCO has a frequency limit about 4 times higher than the frequency limit of the chip itself, so probablu the VCO is running at 4 times the frequency and then divided down into two 90 degree separated clocks at the mixing frequency.

Indeed the same thing can be done using an on-chip PLL.

Then use each rise and fall as a timing pulse.

.... Phil

The reference is in the original posting.

That is normally not a good idea when you want accurate 90 degree phase shift and spectral purity.

Yep. I've done that for crude digital skew, but, for synthesis, symmetry is not guaranteed. ...Jim Thompson

If the phase shifter is digital, internal PLL and dividers, output signal level will not track input RF level. The data sheet is careful to avoid addressing that issue, but I can test it.

And an internal PLL will leak the multiplied Fin out through the package. We see that on those PLL-based "any frequency" crystal oscillators.

If you have 4x clocking, each event of the output square waves is clocked on the same edge; the rising and falling edges are not necessarily symmetric, and that can be a significant error.

DDR memory does the both-edges clocking, but there aren't any Arduino DDR addons, because it's HARD to do that.

It's not hard to connect DDR3 dram to an FPGA, given an FPGA that has the controller block. It's insanely complex inside, but the FPGA takes care of it; we just connect the pins.

We've connected DDR2 to an NXP ARM processor, no problem.