Hi, does anyone know how fast an ARM processor, specifically Atmel's AT91SAM9261 can bit-bang its general-purpose ports? I'm trying to get speeds on the order of 3-6 MHz at a minimum. The idea is to write to a DAC, turn the direction of the 16-bit "bus" around, read from an ADC, and repeat.
I agree, a CPLD or similar device would be better for high-speed jitter-less data transfers; however, I'm seeing pretty long timings when accessing the GPIOs on the ARM that concern me regardless of the source/destination of the signal. Right now it's a struggle to get to
3 MHz or so at a processor clock of 192 MHz, and I'm running with interrupts off and in a tight loop.
After do> You are better off with 2 16 bits uni-directional bus.
Unfortunately I can only use 1 16-bit bus due to other peripherals; it's theoretically possible to put the ADC and DAC on the actual memory bus of the development kit (AT91SAM9261-EK), but it would be a lot more difficult for the fellow making the ADC and DAC boards.
I think that's the way of the world: when you take a device that is a microprocessor (not a microcontroller), and try for hard real time under 1us, you find yourself in 'PC' territory.
Take a CPLD like ATF1502BE, and it should do 16 bit SPI/SSC duplex, so you can read a ADC result, and send a DAC in the same 16 clocks, and use the clock generators to set the rate, which will not all turn to custard, when you enable interrupts....
you really don't want to run the processor databus any further than you have to....
If that is 3MSPS, two ways, you are a long way from ever meeting that SW bit banging. Even a SSC at 48MHz will need care, to keep the frame overhead low. Use a cheap CPLD to wrap the details, and it will pay for itself in saved cabling.
I think you can run the SSC at 48 MHz and this has double buffered DMA support, so you should support 3 Msample/s in each direction using an I2S interface. If your ADC/DAC use a parallel bus, then you can add that CPLD or you can consider the AT91SAM9263, which has a second 16 bit databus and Dual memory to memory DMA support allowing you to easily meet bandwidth needs. The DMA can read/write to bus and to internal 16 kB SDRAM without cycle stealing from the CPU, since it is on the AHB bus matrix.