Hi Paul, Firstly, I apologise if my nomenclature is slightly Xilinx biased, I don't get much chance to use your equally excellent Altera parts in my current work. So, I think I had it in my head originally that _all_ the 8 FFs in a slice could be chosen from to drive _any_ of the LUTs in that slice, such that the delays from FF to LUT were evenly matched. At present this relies on routing outside the slice, and so the delays would be badly characterised. Then I thought it might be possible to up the number of FFs to (say) 16 in a slice to make this more viable. This gives you a 2:1 FF to LUT ratio. But, you need a big switching thingy to get the FFs to the LUTs. Some kind of subset might be fine though. Also, maybe you only need 2 registered inputs per LUT to get a big saving in glitch energy. In thinking this, I assumed that the LUT takes up much more silicon area than the FF, after all the LUT has 16 bits, plus all that address muxing. (Indeed, it's the switching of all that LUT silicon that we want to reduce.) Is that a valid assumption? So, it doesn't make that big a difference to the LE area (see, I know a bit of Alteraese!). In the end we're trading switching a load extra FFs, against saving the glitches in the LUTs. Finally, what 'other power reduction circuitry' are you thinking of? Or is it secret? ;-) Thanks, and Cheers, Syms. p.s. Do you have any comment on my post on the 9th Dec about whether certain LUT inputs are more thirsty than others?
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