making an fpga hot

Hi Paul, Firstly, I apologise if my nomenclature is slightly Xilinx biased, I don't get much chance to use your equally excellent Altera parts in my current work. So, I think I had it in my head originally that _all_ the 8 FFs in a slice could be chosen from to drive _any_ of the LUTs in that slice, such that the delays from FF to LUT were evenly matched. At present this relies on routing outside the slice, and so the delays would be badly characterised. Then I thought it might be possible to up the number of FFs to (say) 16 in a slice to make this more viable. This gives you a 2:1 FF to LUT ratio. But, you need a big switching thingy to get the FFs to the LUTs. Some kind of subset might be fine though. Also, maybe you only need 2 registered inputs per LUT to get a big saving in glitch energy. In thinking this, I assumed that the LUT takes up much more silicon area than the FF, after all the LUT has 16 bits, plus all that address muxing. (Indeed, it's the switching of all that LUT silicon that we want to reduce.) Is that a valid assumption? So, it doesn't make that big a difference to the LE area (see, I know a bit of Alteraese!). In the end we're trading switching a load extra FFs, against saving the glitches in the LUTs. Finally, what 'other power reduction circuitry' are you thinking of? Or is it secret? ;-) Thanks, and Cheers, Syms. p.s. Do you have any comment on my post on the 9th Dec about whether certain LUT inputs are more thirsty than others?

"Paul Leventis (at home)" wrote in message news: snipped-for-privacy@rogers.com...

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Symon
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slice

that the

routing

Then I

slice

you

subset

per LUT

I *think* you mean a CLB everywhere you say a slice (a slice is 2 LUTs

  • 2 FFs + Goo, I believe). I am not too familiar with Xilinx's interslice routing. However, in our products you can get from a FF of one Logic Element (FF + LUT pair) to any other LE/LUT in the same Logic Array Block or LAB (a set of 8/10/16 LEs). The delay from any flop to any LUT in the same LAB is very similar -- for the purposes of power & glitching you could consider these paths to be matched.

Now adding additional FFs... FFs are area hungry (and power hungry...), and it is rare for a design to use all (or even half) the FFs that are already in our parts (with a 1:1 LUT/FF ratio). So these additional FFs would be wasteful of area, and you'd have to ask whether that area was better spent in other ways, or not at all (thus reducing Si cost).

area

muxing.

reduce.)

to the

Once you add in all the goo that comes with a FF (sync clear, asynch clear, clock selection, sync load, etc.) they become surprisingly large. But the second (or more FFs) would not need to be fully featured and so I'll grant you that they wouldn't be huge. But you'd be surprised at the lengths we go to cut even 1% area out of the LE.

Or is

Which ones am I thinking of? That's secret :-) But you can do a literature search on low-power design in FPGAs and ASICs and you'll see there are oodles of ideas out there, some or all of which cause some area bloat in exchange for better power.

certain

Sorry, my news server has been really flaky this month. I've had to resort to using Google groups now. I'll take a look when I get a chance.

Paul Leventis Altera Corp.

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Paul Leventis

Yes, I did mean CLB, thanks for working that out! Thanks for your comments, Syms.

Reply to
Symon

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