how to optimize this comparator for better synthesis result?

What is your synthesis result, and in which way do you want to improve it (e.g. speed vs. area)? What is your design goal? What are your constraints? (time & area)

This is not just a simple comparator, it's a magnitude comparator. There's also an adder included.

Is verilog so type tolerant, that the vector length is not important? You are comparing a 13 bit Vector with a 10 bit vector. VHDL would badly complain about it. But if we just leave it like that, and assume the upper bits to be constantly 0 the resulting circuit will always be a wire to vcc. Thus being optimal for time and area. :-) It only changes when the addition of addr and length (A) generates a carry(C).

0010000000000

Only then the resulting 11 bit vector can be greater than the constant. But how shall the synthesis tool decide whether you want to build an adder with carry or not? Or is there a default mechanism in the arithmetic synthesis of verilog?

have a nice synthesis Eilert

snipped-for-privacy@yahoo.com schrieb:

Eilert's comments are spot-on.

You also might try:

assign len_lt = addr[11:2] + length < 13'h401;

to get rid of the

'h401 - addr = ~addr +1 + 401

If you can compare with 3FF instead of 401 you can save most of the adder.

assign len_lt = length < 13'h400 + ~addr[11:2];

In this formulation only the upper three bits are used in the addition.

Kolja Sulimma

thx, i mean speed.

my solution:

assign addr_pg=addr[11:2]+length;

always @(*) begin if(addr_pg[10]) //11'h400 begin if(|addr_pg[9:0]) tlp_length=start_dist4k; else tlp_length=tlp_length1; end else begin tlp_length=tlp_length1; end end tlp_length is other variable.

it can remove a big comparator.

any better coding style?