debug on top 4 bits, shift register 64 or 28 bits "near ideal" external clock and shift data 4mhz down to 500khz ProAsic3 FPGA
empty FPGA no matter synthesis settings - works correctly full FPGA, 64 bits never worked unless forced global net
28 bits worked one P&R pass, not repeatablesurprising was that pattern 1001 did change to 1011 when the issue was dominant in both cases of 28 and 64 lenghts! ? and it was the same all P&R runs, and always the same 1011 also when the other logic changed a little.
to be honest i did expect that something simple as plain shift register will work properly (no matter what), that is the synthesis and P&R tools make the timings so that there are no violations.
another thing, the actel FPGA is REALLY full, the utilization varied between 81-99% so i was positivly surprised that actel tools never had any issues with the implementation no matter how full the FPGA was. even in runs where only 3 cells was free!
but nothing comes for free - the internal skew on non global net, was a hard hit in terms of wasted time.
as there is no other explanation as net skew, and forcing global buffer fixed the issue i assume that that was it.
the only simulations I did run i did run with xilinx ISIM on the design used as starting point for the actel port, and on the xilinx back-ported version. I was about to try post sims on with actel timings, but as usual modelsim didnt want to start so i did not get that far. actel tools did not give any timing red alerts or anything
Antti