Driving fpga pin out over long cable

The natsemi drivers might seem an over-kill, but they do give you tracking with your clock system, and since that sounds like it rather matters, anything you a) already know and b) tracks what you already use

sounds to me like a simple, elegant solution ?

Another scheme for global sync, (but that some systems cannot tolerate), is to send a break in the clock stream - can be as simple as a single missing pulse. Gives you a time-Zero, and all units thereafter are in-phase.

-jg

There also are the AnalogDevices ADum1400 family of magnetocouplers, some of which are spec'ed for 100MBit.

Rene

One more vote for LVDS. Here's an app note for TI M-LVDS technology.

Basically they say -6dB at 30m over UTP for 100 Mbps, and a little over 10% jitter at 50m. I expect you may be able to do better with co-ax cable -- look for a type with low-loss dielectric and, for lower power consumption, higher characteristic impedance -- co-ax goes upto about 100ohm. You will need to be careful about ground differences between the two ends.

Regards,

-rajeev-

How about this weird idea: Don't send a pulse, send an edge. Your attenuation might provide a little phase shift but it would be pretty easy to alter the phase to match the clocks. Rather than a smeared pulse with low high-level amplitudes, you get a full transition with a consistent 50% point.

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Great solution, Peter. Some years ago I used this scheme to communicate two systems ... until I change to Manchester ;-).

Anyway, has someone thought that the signal needs about 250 ns (25 clock cycles at 100 MHz) to fly from one board to the others. 50m are

And you want us to give you a link to a cheap, or better to a free time machine ?

Rene

Yes, but the OP did say the cable lengths were equal ?

Gabor Szakacs wrote: > To go one step further with Peter's idea, you can AC couple if instead > of sending an occasional "pulse" (one cycle of 70% high) you send a > "square wave" of say 50 cycles of 30% high followed by 50 cycles of 70% > high. This gives you synchronizing events at each edge of the wave and > keeps the DC balance over the period of 1uS.

This is how TV frame sync pulses are sent, and is a good idea.

-jg

That's a lot of wasted overhead time, and I threw in the warning about the need for dc coupling as a afterthought. Why would anybody use ac coupling?

Regard>

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ac coupling could allow improved ground tolerance ?. The 50m is pushing LVDS common mode a little.

ac coupling would have minor effects, if the rolloff was right.

- a handfull of skewed clocks would pass OK. What COULD be important, is the general LPF actions of longish cables, and the eye distortions that causes. Perhaps merit in a couplet of 30/70/70/30 as a minimal disturbance sync scheme ( no nett low frequency content) ? Because it uses a common clock, and can define a start edge explicitly, this sync-on-clock scheme can deliver an order of magnitude improvement over the OPs first jitter target, so it pays to think just how good it can get.

-jg

Some great thoughts and information, thank you!

Unfortunately I don't have much control over the master clock - it is derived from an OCXO, goes through a power splitter, then is sent down the cables using the Natsemi chipset (provides active equalisation at the receiver based on high frequency content from which it can approximate the cable length and hence the equalisation curve required). This clock must be as low phase noise as possible because it is also used to clock other components (e.g. ADC), and a clock derived from an FPGA (over which I could have control) would have much worse jitter.

I like the idea of level sensing rather than edge sensing as the events are only occasional - it just means that the threshold crossing should be stable and occur during the same clock cycle at each board. To that end, the TI M-LVDS chips look a good bet - high drive level, low impedance. They do however specify a ground voltage difference of less than 1V. I can connect the grounds of the power supplies for each board together so that should provide a fairly low impedance path.. I will try it out and report back to the group.

Many thanks for your help Tom